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W65C51S Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part No. W65C51S
Description  Asynchronous Communications Interface Adapter (ACIA)
Download  26 Pages
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Maker  ETC1 [List of Unclassifed Manufacturers]

W65C51S Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

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Figure 3 ACIA Internal Organization
A block diagram of the ACIA is presented in Figure 2
followed by a description of each functional element of the
The Data Bus Buffer interfaces the system data lines to the
internal data bus. The Data Bus Buffer is bi-directional.
When the RWB line is high and the chip is selected, the Data
Bus Buffer passes the data from the system data lines to the
ACIA internal data bus. When the RWB line is low and the
chip is selected, the Data Bus Buffer writes the data from the
internal data bus to the system data bus.
The Interrupt Logic will cause the IRQB line to the
microprocessor to go low when conditions are met that
require the attention of the microprocessor. The conditions
which can cause an interrupt will set bit 7 and the appropriate
bit of bits 3 through 6 in the Status Register, if enabled. Bits
5 and 6 correspond to the Data Carrier Detect (DCDB) logic
and the Data Set Ready (DSRB) logic.
Bits 3 and 4
correspond to the Receiver Data Register full and the
Transmitter Data Register empty conditions.
conditions can cause an interrupt request if enabled by the
Command Register.
The I/O Control Logic controls the selection of internal
registers in preparation for a data transfer on the internal data
bus and the direction of the transfer to or from the register.
The registers are selected by the Register Select (RS1, RS0)
and Read/Write (RWB) lines as described later in Table 1.
The Timing and Control logic controls the timing of data
transfers on the internal data bus and the registers, the Data
Bus Buffer and the microprocessor data bus and hardware
reset features.
Timing is controlled by the system PHI2 clock input. The
chip will perform data transfers to or from the microcomputer
data bus during the PHI2 high period when selected.
The Timing and Control Logic will initialize all registers
when the Reset (RESB) line goes low. See the individual
register description for the state of the registers following a
hardware reset.
These registers are used as temporary data storage for the
ACIA Transmit and Receive Circuits. Both the Transmitter
and Receiver are selected by a Register Select 0 (RS0) and
Register Select 1 (RS1) low condition. The Read/Write
(RWB) line determines which actually uses the internal data
bus; the Transmitter Data Register is write only and the
Receiver Data Register is read only.
Bit 0 is the first bit to be transmitted from the Transmitter
Data Register (least significant bit first). The higher order
bits follow in order. Unused bits in this register are “don’t
The Receiver Data Register holds the first received data bit in
bit 0 (least significant bit first). Unused high-order bits are
“0”. Parity bits are not contained in the Receiver Data
Register. They are stripped off after being used for parity

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