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MAX9000 Datasheet(PDF) 29 Page - Altera Corporation |
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MAX9000 Datasheet(HTML) 29 Page - Altera Corporation |
29 / 42 page Altera Corporation 29 MAX 9000 Programmable Logic Device Family Data Sheet tPD1 Row I/O pin input to row I/O pin output C1 = 35 pF (2) 10.0 15.0 20.0 ns tPD2 Column I/O pin input to column I/O pin output C1 = 35 pF (2) EPM9320A 10.8 ns EPM9320 16.0 23.0 ns EPM9400 16.2 23.2 ns EPM9480 16.4 23.4 ns EPM9560A 11.4 ns EPM9560 16.6 23.6 ns tFSU Global clock setup time for I/O cell 3.0 5.0 6.0 ns tFH Global clock hold time for I/O cell 0.0 0.0 0.0 ns tFCO Global clock to I/O cell output delay C1 = 35 pF 1.0 (3) 4.8 1.0 (3) 7.0 1.0 (3) 8.5 ns tCNT Minimum internal global clock period (4) 6.9 8.5 10.0 ns fCNT Maximum internal global clock frequency (4) 144.9 117.6 100.0 MHz |
Similar Part No. - MAX9000 |
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Similar Description - MAX9000 |
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