S29JL064H70TAI003 datasheet(11/64 Pages) SPANSION

Part #	S29JL064H70TAI003

Description	64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory

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Manufacturer	SPANSION [SPANSION]

Direct Link	http://www.spansion.com

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11 / 64 page

March 26, 2004 S29JL064HA1

S29JL064H

11

Pre l i m i n a r y

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or

word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only

data I/O pins DQ7–DQ0 are active and controlled by CE# and OE#. The data I/

O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the

LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE#

pins to VIL. CE# is the power control and selects the device. OE# is the output

control and gates array data to the output pins. WE# should remain at VIH. The

BYTE# pin determines whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up,

or after a hardware reset. This ensures that no spurious alteration of the memory

content occurs during the power transition. No command is necessary in this

mode to obtain array data. Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data on the device data

outputs. Each bank remains enabled for read access until the command register

contents are altered.

Refer to the AC Read-Only Operations table for timing specifications and to 14 for

the timing diagram. ICC1 in the DC Characteristics table represents the active cur-

rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data

to the device and erasing sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines whether the device accepts

program data in bytes or words. Refer to “Word/Byte Configuration” for more

information.

The device features an Unlock Bypass mode to facilitate faster programming.

Once a bank enters the Unlock Bypass mode, only two write cycles are required

to program a word or byte, instead of four. The “Byte/Word Program Command

Sequence” section has details on programming data to the device using both

standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.

Table 3 indicates the address space that each sector occupies. Similarly, a “sector

address” is the address bits required to uniquely select a sector. The “Command

Definitions” section has details on erasing a sector or the entire chip, or suspend-

ing/resuming the erase operation.

The device address space is divided into four banks. A “bank address” is the ad-

dress bits required to uniquely select a bank.

ICC2 in the DC Characteristics table represents the active current specification for

the write mode. The AC Characteristics section contains timing specification ta-

bles and timing diagrams for write operations.

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