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S29JL064H55BFN000 Datasheet(PDF) 4 Page - SPANSION

Part # S29JL064H55BFN000
Description  64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S29JL064H55BFN000 Datasheet(HTML) 4 Page - SPANSION

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4S29JL064H
S29JL064HA1 March 26, 2004
Pr el i m i n ary
Table Of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 10
Table 1. S29JL064H Device Bus Operations ..........................10
Requirements for Reading Array Data ............................................11
Writing Commands/Command Sequences .................................... 11
Accelerated Program Operation ...................................................... 12
Autoselect Functions ............................................................................ 12
Simultaneous Read/Write Operations with Zero Latency ....... 12
Automatic Sleep Mode ......................................................................... 13
RESET#: Hardware Reset Pin ............................................................ 13
Output Disable Mode ........................................................................... 14
Table 2. S29JL064H Sector Architecture ...............................15
Table 3. Bank Address .......................................................18
Autoselect Mode ...................................................................................18
Table 5. S29JL064H Autoselect Codes, (High Voltage
Method) .........................................................................19
Sector/Sector Block Protection and Unprotection .................... 19
Table 6. S29JL064H Boot Sector/Sector Block Addresses for
Protection/Unprotection .....................................................20
Write Protect (WP#) ........................................................................... 21
Table 7. WP#/ACC Modes ..................................................21
Temporary Sector Unprotect ........................................................... 21
Figure 1. Temporary Sector Unprotect Operation................... 22
Figure 2. In-System Sector Protect/Unprotect Algorithms ....... 23
SecSi™ (Secured Silicon) Sector
Flash Memory Region .......................................................................... 24
Figure 3. SecSi Sector Protect Verify ................................... 25
Hardware Data Protection ................................................................ 25
Low VCC Write Inhibit ...................................................................... 25
Write Pulse “Glitch” Protection ...................................................... 26
Logical Inhibit ......................................................................................... 26
Power-Up Write Inhibit ..................................................................... 26
Common Flash Memory Interface (CFI) . . . . . . .26
Command Definitions . . . . . . . . . . . . . . . . . . . . . .30
Reading Array Data ............................................................................. 30
Reset Command ................................................................................... 30
Autoselect Command Sequence ....................................................... 31
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence ............................................................................. 31
Byte/Word Program Command Sequence .................................... 31
Unlock Bypass Command Sequence ............................................... 32
Figure 4. Program Operation .............................................. 33
Chip Erase Command Sequence .......................................................33
Sector Erase Command Sequence .................................................. 34
Figure 5. Erase Operation .................................................. 35
Erase Suspend/Erase Resume Commands .....................................35
Write Operation Status . . . . . . . . . . . . . . . . . . . . .38
DQ7: Data# Polling .............................................................................. 38
Figure 6. Data# Polling Algorithm ....................................... 39
DQ6: Toggle Bit I ..................................................................................40
Figure 7. Toggle Bit Algorithm ............................................ 41
DQ2: Toggle Bit II ................................................................................. 41
Reading Toggle Bits DQ6/DQ2 ........................................................ 42
DQ5: Exceeded Timing Limits .......................................................... 42
DQ3: Sector Erase Timer .................................................................. 42
Table 9. Write Operation Status ......................................... 43
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 44
Figure 8. Maximum Negative Overshoot Waveform................ 44
Figure 9. Maximum Positive Overshoot Waveform ................. 44
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .44
Industrial (I) Devices ............................................................................ 44
Extended (N) Devices ......................................................................... 44
VCC Supply Voltages ............................................................................44
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 45
CMOS Compatible ............................................................................... 45
Figure 10. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ................................................. 46
Figure 11. Typical ICC1 vs. Frequency .................................. 46
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 12. Test Setup ....................................................... 47
Key To Switching Waveforms . . . . . . . . . . . . . . . .47
Figure 13. Input Waveforms and Measurement Levels............ 47
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .48
Read-Only Operations ......................................................................48
Figure 14. Read Operation Timings...................................... 48
Hardware Reset (RESET#) ................................................................49
Figure 15. Reset Timings ................................................... 49
Word/Byte Configuration (BYTE#) ................................................ 50
Figure 16. BYTE# Timings for Read Operations ..................... 51
Figure 17. BYTE# Timings for Write Operations..................... 51
Erase and Program Operations ........................................................ 52
Figure 18. Program Operation Timings ................................. 53
Figure 19. Accelerated Program Timing Diagram ................... 53
Figure 20. Chip/Sector Erase Operation Timings.................... 54
Figure 21. Back-to-back Read/Write Cycle Timings ................ 55
Figure 22. Data# Polling Timings (During Embedded
Algorithms)...................................................................... 55
Figure 23. Toggle Bit Timings (During Embedded
Algorithms)...................................................................... 56
Figure 24. DQ2 vs. DQ6..................................................... 56
Temporary Sector Unprotect .......................................................... 57
Figure 25. Temporary Sector Unprotect Timing Diagram......... 57
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ................................................. 58
Alternate CE# Controlled Erase and Program Operations .... 59
Figure 27. Alternate CE# Controlled Write (Erase/Program)
Operation Timings............................................................. 60
Erase And Programming Performance . . . . . . . . 61
TSOP & BGA Pin Capacitance . . . . . . . . . . . . . . 61
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 62
FBE063—63-Ball Fine-Pitch Ball Grid Array (BGA)
12 x 11 mm package ............................................................................... 62
TS 048—48-Pin Standard TSOP ...................................................... 63
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 64


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