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STA8089FG Datasheet(PDF) 17 Page - STMicroelectronics

Part # STA8089FG
Description  Fully integrated GPS/Galileo/GLONASS/BeiDou/QZSS receiver with embedded RF and in-package Flash
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA8089FG Datasheet(HTML) 17 Page - STMicroelectronics

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DocID027175 Rev 8
17/34
STA8089FG
General description
33
SSP features
The SSP has the following features:
Parallel-to-serial conversion on data written to an internal 32-bit wide, 32-location deep
transmit FIFO
Serial-to-parallel conversion on received data, buffering it in a 32-bit wide, 32-location
deep receive FIFO
Programmable data frame size from 4 to 32 bits,
Programmable clock bit rate and prescaler
Programmable clock phase and polarity in SPI mode
3.4.3
UART
The UARTx (x = 0|1|2) performs serial-to-parallel conversion on data asynchronously
received from a peripheral device on UARTx_RX pin, and parallel-to-serial conversion on
data written by CPU for transmission on UARTx_TX pin. The transmit and receive paths are
buffered with internal FIFO memories allowing up to 64 data byte for transmission, and 64
data byte with 4-bit status (break, frame, parity, and overrun) for receive.
UART features
The UARTx (x = 0|1|2) are Universal Asynchronous Receiver/Transmitter that support much
of the functionality of the industry-standard 16C650 UART. The main features are:
Programmable baud rates up to UARTCLK / 16 (1.5 Mbps with UARTCLK at 24 MHz),
or up to UARTCLK / 8 (3.0 Mbps with UARTCLK at 24 MHz), with fractional baud-rate
generator
5, 6, 7 or 8 bits of data
Even, odd, stick or no-parity bit generation and detection
1 or 2 stop bit generation
Support of software flow control using programmable Xon/Xoff characters
False start bit detection
Line break generation and detection
Separate 8-bit wide, 64-deep transmit FIFO and 12-bit wide, 64-deep receive FIFO
Programmable FIFO disabling for 1-byte depth data path
These UARTs vary from industry-standard 16C650 on some minor points which are:
Receive FIFO trigger levels
The internal register map address space, and the bit function of each register differ
The deltas of the modem status signals are not available
1.5 stop bits is not supported
Independent receive clock feature is not supported
3.4.4
Flash
The STA8089FG integrates 16Mbits of Flash Memory. This eliminates the need external
Flash simplifying the routing associated to integrate a GPS receiver into a customer board.


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