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CAT24C03 Datasheet(PDF) 2 Page - Catalyst Semiconductor

Part No. CAT24C03
Description  2-Kb I2C CMOS Serial EEPROM with Partial Array Write Protection
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Maker  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
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CAT24C03 Datasheet(HTML) 2 Page - Catalyst Semiconductor

 
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CAT24C03
2
Doc. No. 1113, Rev. A
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
-65°C to +150°C
Voltage on Any Pin with Respect to Ground(1)
-0.5 V to +6.5 V
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS(2)
Symbol Parameter
Min
Units
NEND(*) Endurance
1,000,000
Program/ Erase Cycles
TDR
Data Retention
100
Years
(*) Page Mode, VCC = 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Test Conditions
Min
Max
Units
ICC
Supply Current
Read or Write at 400 kHz
1
mA
ISB
Standby Current
All I/O Pins at GND or VCC
2
μA
IL
I/O Pin Leakage
Pin at GND or VCC
2
μA
VIL
Input Low Voltage
-0.5
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7 VCC + 0.5
V
VOL1
Output Low Voltage
VCC > 2.5 V, IOL = 3.0 mA
0.4
V
VOL2
Output Low Voltage
VCC > 1.8 V, IOL = 1.0 mA
0.2
V
PIN IMPEDANCE CHARACTERISTICS
TA = 25°C, f = 400 kHz, VCC = 5 V
Symbol Parameter
Conditions
Min
Max
Units
CIN(2)
SDA I/O Pin Capacitance
VIN = 0 V
8
pF
CIN(2)
Input Capacitance (other pins)
VIN = 0 V
6
pF
ZWPL
WP Input Low Impedance
VIN < 0.5 V
5
70
ILWPH
WP Input High Leakage
VIN > VCC x 0.7
2
μA
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.


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