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CAT24C03 Datasheet(PDF) 3 Page - Catalyst Semiconductor

Part No. CAT24C03
Description  2-Kb I2C CMOS Serial EEPROM with Partial Array Write Protection
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Maker  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
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CAT24C03 Datasheet(HTML) 3 Page - Catalyst Semiconductor

 
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CAT24C03
3
Doc No. 1113, Rev. A
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
A.C. CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
1.8 V - 5.5 V
2.5 V - 5.5 V
Units
Min
Max
Min
Max
FSCL
Clock Frequency
100
400
kHz
TI(1)
Noise Suppression Time Constant at
SCL, SDA Inputs
0.1
0.1
μs
tAA(2)
SCL Low to SDA Data Out
3.5
0.9
μs
tBUF(1)
Time the Bus Must be Free Before a
New Transmission Can Start
4.7
1.3
μs
tHD:STA
Start Condition Hold Time
4
0.6
μs
tLOW
Clock Low Period
4.7
1.3
μs
tHIGH
Clock High Period
4
0.6
μs
tSU:STA
Start Condition Setup Time
4.7
0.6
μs
tHD:DAT
Data In Hold Time
0
0
μs
tSU:DAT
Data In Setup Time
0.25
0.1
μs
tR(1)
SDA and SCL Rise Time
1
0.3
μs
tF(1)
SDA and SCL Fall Time
0.3
0.3
μs
tSU:STO
Stop Condition Setup Time
4
0.6
μs
tDH
Data Out Hold Time
0.1
0.1
μs
tWR
Write Cycle Time
5
5
ms
tPU(1), (3)
Power-up to Ready Mode
1
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) For timing measurements the SDA line capacitance is ~ 100 pF; the SCL input is driven with rise and fall times of < 50 ns; the SDA I/O
is pulled-up by a 3 mA current source; input driving signals swing from 20% to 80% of VCC. Output level reference levels are 30% and
respectively 70% of VCC.
(3) tPU is the delay required from the time VCC is stable until the device is ready to accept commands.
Power-On Reset (POR)
The CAT24C03 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
The CAT24C03 will power up into Standby mode after
VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
The POR circuitry triggers at the minimum VCC level
required for proper initialization of the internal state
machines. The POR trigger level automatically tracks the
internal CMOS device thresholds, and is naturally well
below the minimum recommended VCC supply voltage.


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