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SI4567DY Datasheet(PDF) 1 Page - Vaishali Semiconductor

Part No. SI4567DY
Description  Dual N- and P-Channel 40-V (D-S) MOSFET
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Maker  VAISH [Vaishali Semiconductor]
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SI4567DY Datasheet(HTML) 1 Page - Vaishali Semiconductor

   
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Vishay Siliconix
SPICE Device Model Si4567DY
Dual N- and P-Channel 40-V (D-S) MOSFET
CHARACTERISTICS
• N- and P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n- and p-channel vertical DMOS.
The
subcircuit
model
is
extracted
and
optimized
over
the
−55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate
drive. The saturated output impedance is best fit at the gate bias
near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
1
www.vishay.com
Document Number: 74147
S-60243
Rev. A, 20-Feb-06


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