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LM1270NA Datasheet(PDF) 12 Page - National Semiconductor (TI) |
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LM1270NA Datasheet(HTML) 12 Page - National Semiconductor (TI) |
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12 / 27 page  Video Detection (Continued) registers have been enabled either by previously reading the D_CNTLS register, or by writing a zero to the STAT bit of the D_CNTL register. Only one line of data is allowed per field. After the clock stream of 72 pulses has been detected and accepted and the data stored in registers 2E-36, no more data will be accepted until after the registers have been reset. This is to allow time for the microcontroller to access the data on the I 2C bus. If the LIMIT bit in the TEST1 register is set to a “1” (default value), then the data must arrive during the pro- grammed vertical blanking period. Any data arriving outside of this will be ignored. If the bit is set to a “0”, then the data may arrive anytime, even within the active video area. The maximum data rate is half of the clock rate. The data is clocked by the trailing edge of the clock. The clock rate should be chosen to allow all 72 pixels to occur within the normal horizontal active video timing. INTERRUPT SIGNAL Pin 15, the Blanking/Interrupt pin, can be set to output an interrupt signal by bit 2 of register 39. The default value for this bit is “0”, setting pin 15 for a blanking output signal. However, if bit 2 is set to a “1” then pin 15 outputs an interrupt signal. When the LM1270 is instructed to read the information sent by video, then this signal goes low. Once the clock stream of 72 pulses has occurred, then the inter- rupt signal goes high again at the leading edge of H Sync. The interrupt signal remains high until another request to read the video information is received. Some microcontrol- lers may require an interrupt signal. Setting pin 15 to output an interrupt signal will provide the needed signal for these systems. In this mode of operation the vertical blanking signal will be unavailable; however, vertical blanking may still be added to the video outputs. Note that bit 1 of register 1 does change the polarity of the interrupt signal. Parameter Timing T CLK 50 ns T CLK-H 25 ns T CLK-L 25 ns T SETUP-H 13 ns T SETUP-L 13 ns Emphasis MEASURING EMPHASIS Two adjustments are available to optimize the emphasis in the Hi-Brite window for the various timing modes and bright- ness levels. One adjustment is the center frequency and the other adjustment is the amount of overshoot. Referring to Figure 7 the overshoot is the ratio of the overshoot voltage to the video level after the emphasis has settle out of the output signal. The typical output level is 900 mV and the typical overshoot is about 20%. The peak measurement is taken 9 ns from the rising edge. This delay gives a more accurate peak measurement by avoiding any ringing that may occur at the rising edge. Overshoot is defined in percent as: Bits 0 to 2 in register 0B control the emphasis. When a “4” is programmed into these bits the overshoot is typically 11%. A “0” will give no overshoot in the Hi-Brite window. Shown below in Figure 8 is how the center frequency is measured. The center frequency is actually expressed as the time it takes the overshoot to settle to within 5% of the DC level of the pulse. 20063523 FIGURE 6. Timing Parameters 20063525 FIGURE 7. Overshoot Measurement 20063526 FIGURE 8. Center Frequency Measurement www.national.com 12 |
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