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ADE7761 Datasheet(PDF) 19 Page - Analog Devices |
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ADE7761 Datasheet(HTML) 19 Page - Analog Devices |
19 / 28 page ADE7761 Rev. A | Page 19 of 28 Table 5. F1–4 Frequency Selection S1 S0 F1–4 (Hz)1 OSC/CLKIN2 0 0 1.72 OSC/218 0 1 3.44 OSC/217 1 0 6.86 OSC/216 1 1 13.7 OSC/215 1 Values are generated using the nominal frequency of 450 kHz. 2 F1–4 are a binary fraction of the master clock and, therefore, vary with the internal oscillator frequency (OSC). Frequency Output CF The pulse output calibration frequency (CF) is intended for use during calibration. The output pulse rate on CF can be up to 2048 times the pulse rate on F1 and F2. The lower the F1–4 frequency selected, the higher the CF scaling. Table 6 shows how the two frequencies are related, depending on the states of the logic inputs S0, S1, and SCF. Because of its relatively high pulse rate, the frequency at this logic output is proportional to the instantaneous active power. As with F1 and F2, the frequency is derived from the output of the low-pass filter after multiplication. However, because the output frequency is high, this active power information is accumulated over a much shorter time. Therefore, less averaging is carried out in the digital-to-frequency conversion. With much less averaging of the active power signal, the CF output is much more responsive to power fluctuations (see Figure 20). Table 6. Relationship between CF and F1, F2 Frequency Outputs SCF S1 S0 F1–4 (Hz) CF Frequency Output 1 0 0 1.72 128 × F1, F2 0 0 0 1.72 64 × F1, F2 1 0 1 3.44 64 × F1, F2 0 0 1 3.44 32 × F1, F2 1 1 0 6.86 32 × F1, F2 0 1 0 6.86 16 × F1, F2 1 1 1 13.7 16 × F1, F2 0 1 1 13.7 2048 × F1, F2 Example In this example, if ac voltages of ±660 mV peak are applied to V1 and V2, then the expected output frequency on CF, F1, and F2 is calculated as follows: F1–4 = 1.7 Hz, SCF = S1 = S0 = 0 V1rms = rms of 660 mV peak ac = 0.66/√2 V V2rms = rms of 660 mV peak ac = 0.66/√2 V VREF = 2.5 V (nominal reference value) Note that if the on-chip reference is used, actual output frequencies may vary from device to device due to a reference tolerance of ±8%. Hz 0 . 22 64 Hz 34 . 0 5 . 2 2 2 Hz 72 . 1 66 . 0 66 . 0 70 . 5 2 1 2 = × − = = × × × × × = − F F Frequency CF Frequency F F 2 1 As can be seen from these two example calculations, the maximum output frequency for ac inputs is always half of that for dc input signals. Table 7 shows a complete listing of all maximum output frequencies for ac signals. Table 7. Maximum Output Frequency on CF, F1, and F2 for AC Inputs SCF S1 S0 F1, F2 Maximum Frequency (Hz) CF Maximum Frequency (Hz) CF to F1 Ratio 1 0 0 0.34 43.52 128 0 0 0 0.34 21.76 64 1 0 1 0.68 43.52 64 0 0 1 0.68 21.76 32 1 1 0 1.36 43.52 32 0 1 0 1.36 21.76 16 1 1 1 2.72 43.52 16 0 1 1 2.72 5570 2048 FAULT DETECTION The ADE7761 incorporates a novel fault detection scheme that warns of fault conditions and allows the ADE7761 to continue accurate billing during a fault event. The ADE7761 does this by continuously monitoring both the phase and neutral (return) currents. A fault is indicated when these currents differ by more than 6.25%. However, even during a fault, the output pulse rate on F1 and F2 is generated using the larger of the two currents. Because the ADE7761 looks for a difference between the voltage signals on V1A and V1B, it is important that both current trans- ducers be closely matched. On power-up, the output pulse rate of the ADE7761 is pro- portional to the product of the voltage signals on V1A and Channel 2. If there is a difference of greater than 6.25% between V1A and V1B on power-up, the fault indicator (FAULT) becomes active after about 1 s. In addition, if V1B is greater than V1A, the ADE7761 selects V1B as the input. The fault detection is automatically disabled when the voltage signal on Channel 1 is less than 0.3% of the full-scale input range. This eliminates false detection of a fault due to noise at light loads. |
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