pin low and then returning it to high to enable the
Pak I. This is useful if you are connecting more
than one Pak to the same data and clock lines.
You'll need to use the enable pin then anyway, and
it makes sure that the selected Pak is always in a
known state. Using the data sequence method may
be unreliable when using multiple Paks together.
Finally, you can force a hardware reset by bringing
the reset pin low. Holding the clock pin high for
more than 2400mS will also force a reset. This
might be useful if your circuit generates a
hardware reset signal based on a brown-out
detector or other master reset circuit. Normally,
you'll just connect the reset pin to the +5V supply
and allow the Pak I to reset itself on power up. If
you do want to drive this pin, make sure that it is
at 5V for normal operation. You can use a reset
switch or other device if you pull up the reset pin
with a 10K-22K resistor.
Communications
There are several schemes you can use to
communicate with the Pak I. All of them revolve
around a synchronous protocol involving a clock
pin and 1 or 2 data pins. Data is shifted most
significant bit first, and samples at the rising edge
of the clock. All signals are positive logic (that is,
a 1 is a high logic level). The Pak I exposes a
separate input (SIN) and output (SOUT) pins for
hosts that can't easily handle bi-directional I/O
lines. However, for hosts like the Stamp or PIC, it
is a simple matter to tie these lines together since
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