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MX28F640C3T Datasheet(PDF) 2 Page - Macronix International

Part No. MX28F640C3T
Description  64M-BIT [4M x16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
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Maker  MCNIX [Macronix International]
Homepage  http://www.macronix.com
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MX28F640C3T Datasheet(HTML) 2 Page - Macronix International

 
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MX28F640C3T/B
REV. 0.6, AUG. 20, 2003
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX28F640C3T/B uses a 2.7V~3.6V VCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
The dedicated VPP pin gives complete data protection
when VPP< VPPLK.
A Command User Interface (CUI) serves as the inter-
face between the system processor and internal opera-
tion of the device. A valid command sequence written to
the CUI initiates device automation. An internal Write
State Machine (WSM) automatically executes the algo-
rithms and timings necessary for erase, full chip erase,
word write and sector lock/unlock configuration opera-
tions.
A sector erase operation erases one of the device's 32K-
word sectors typically within 1.0s, 4K-word sectors typi-
cally within 0.5s independent of other sectors. Each sec-
tor can be independently erased minimum 100,000 times.
Sector erase suspend mode allows system software to
suspend sector erase to read or write data from any other
sector.
Writing memory data is performed in word increments of
the device's 32K-word sectors typically within 0.8s and
4K-word sectors typically within 0.1s.Word program sus-
pend mode enables the system to read data or execute
code from any other memory array location.
MX28F640C3T/B features with individual sectors lock-
ing by using a combination of bits thirty-nine sector lock-
bits and WP, to lock and unlock sectors.
The status register indicates when the WSM's sector
erase, full chip erase, word program or lock configura-
tion operation is done.
The access time is 90/120ns (tELQV) over the operat-
ing temperature range (-40°C to +80°C) and VCC supply
voltage range of 2.7V~3.6V.
MX28F640C3T/B's power saving mode feature substan-
tially reduces active current when the device is in static
mode (addresses not switching). In this mode, the typi-
cal ICCS current is 7uA (CMOS) at 3.0V VCC.
As CE and RESET are at VCC, ICC CMOS standby
mode is enabled. When RESET is at GND, the reset
mode is enabled which minimize power consumption and
provide data write protection.
A reset time (tPHQV) is required from RESET switching
high until outputs are valid. Similarly, the device has a
wake time (tPHEL) from RESET-high until writes to the
CUI are recognized. With RESET at GND, the WSM is
reset and the status register is cleared.


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