Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MN86063 Datasheet(PDF) 6 Page - Panasonic Semiconductor

Part No. MN86063
Description  High-Speed CODEC LSI for Facsimile Images
Download  10 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  PANASONIC [Panasonic Semiconductor]
Homepage  http://www.panasonic.com/industrial/
Logo 

MN86063 Datasheet(HTML) 6 Page - Panasonic Semiconductor

 
Zoom Inzoom in Zoom Outzoom out
 6 / 10 page
background image
MN86063
For Communications Equipment
Pin Descriptions (continued)
78
ID15
I/O
Image data. These pins form a bus for bidirectional transfers of image data.
79
ID14
Tristate
80
ID13
81
ID12
82
ID11
83
ID10
84
ID9
85
ID8
86
ID7
87
ID6
88
ID5
89
ID4
90
ID3
91
ID2
92
ID1
93
ID0
41
IHREQ
O
Image bus request. This output pin indicates a request for control of the
image bus.
42
IHACK
I
Image bus acknowledge. This input pin indicates when the chip can seize
control of the image bus.
49
IREADY
I
Image data acknowledge. This input pin indicates the end of the read/
write operation.
52
IMUE
O
Image memory upper byte enable. This output pin specifies whether the
Tristate
data from pins ID15–ID8 is effective.
53
IMLE
O
Image memory lower byte enable. This output pin specifies whether the
Tristate
data from pins ID7–ID0 is effective.
45
IMR
O
Image memory read. This output pin indicates a read from the address on
Tristate
the image address bus.
47
IMW
O
Image memory write. This output pin indicates a write to the address on
Tristate
the image address bus.
55
DSTR0
O
DMA start 0. This output indicates that the chip is ready for a DMA
transfer from an I/O device to memory.
54
DSTR1
O
DMA start 1. This output indicates that the chip is ready for a DMA
transfer from memory to an I/O device.
44
DREQ0
I
DMA request 0. This input pin indicates a request for a DMA transfer
from an I/O device to memory.
43
DREQ1
I
DMA request 1. This input pin indicates a request for a DMA transfer
from memory to an I/O device.
56
DACK0
O
DMA acknowledge 0. This output pin gives the response to the DREQ0
signal, initiating a DMA transfer from an I/O device to memory.
57
DACK1
O
DMA acknowledge 1. This output pin gives the response to the DREQ1
signal, initiating a DMA transfer from memory to an I/O device.
Image Bus (continued)
Pin No.
Symbol
I/O
Function Description


Html Pages

1  2  3  4  5  6  7  8  9  10 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn