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534CD622M080BGR Datasheet(PDF) 3 Page - Silicon Laboratories |
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534CD622M080BGR Datasheet(HTML) 3 Page - Silicon Laboratories |
3 / 12 page Si550 Preliminary Rev. 0.3 3 Table 3. CLK± Output Frequency Characteristics Parameter Symbol Test Condition Min Typ Max Units Nominal Frequency1,2,3 fO LVDS/CML/LVPECL 10 — 945 MHz CMOS 10 — 160 Temperature Stability1,4 ∆f/fO TA = –40 to +85 ºC –20 –50 –100 — — — +20 +50 +100 ppm Absolute Pull Range1,4 APR ±25 — ±150 ppm Aging Frequency drift over 15 year life. —— ±10 ppm Power up Time5 tOSC —— 10 ms Notes: 1. See Section 3. "Ordering Information" on page 8 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Nominal output frequency set by VCNOM =3/8 xVDD. 4. Selectable parameter specified by part number. 5. Time from power up or tristate mode to fO. Table 4. CLK± Output Levels and Symmetry Parameter Symbol Test Condition Min Typ Max Units LVPECL Output Option1 VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.5 — 0.93 VPP LVDS Output Option2 VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.32 0.40 0.50 VPP CML Output Option2 VO mid-level — VDD – 0.75 — V VOD swing (diff) 0.70 0.95 1.20 VPP CMOS Output Option3 VOH IOH =32mA 0.8 x VDD — VDD V VOL IOL =32mA —— 0.4 Rise/Fall time (20/80%) tR, tF LVPECL/LVDS/CML — — 350 ps CMOS with CL = 15 pF — 1 — ns |
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