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532HA622M080BGR Datasheet(PDF) 2 Page - Silicon Laboratories |
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532HA622M080BGR Datasheet(HTML) 2 Page - Silicon Laboratories |
2 / 10 page Si532 2 Preliminary Rev. 0.3 1. Electrical Specifications Table 1. Si532 Electrical Specifications Parameter Min Typ Max Units Notes Frequency Nominal Frequency LVDS/CML/LVPECL CMOS 10 10 — — 945 160 MHz Specified at time of order by P/N. Also available in bands from 970 to 1134 MHz and 1213 to 1417 MHz. Initial Accuracy –1.5 — 1.5 ppm Measured at +25 °C at time of ship- ping Temperature Stability –20 –50 — — +20 +50 ppm Selectable option by P/N. See Section 4. "Ordering Information" on page 7. Aging — — ±10 ppm Frequency drift over projected 15 year life Outputs Symmetry 45 — 55 % LVPECL: VDD – 1.3 V (differential) LVDS: 1.25 V (differential) CMOS: VDD/2 RMS Jitter for FOUT > 500 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz — — 0.27 0.30 — — ps FOUT > 500 MHz Differential Modes: LVPECL/LVDS/CML RMS Jitter for FOUT of 125 to 500 MHz 12 kHz to 20 MHz —0.5 — ps 125 < FOUT < 500 MHz Differential Modes: LVPECL/LVDS/CML Period Jitter for FOUT <160 MHz Peak-to-Peak RMS — — 5 1 — — ps Any output N = 1000 cycles LVPECL Output Option mid-level swing (diff) swing (single-ended) VDD – 1.42 1.1 0.50 — — — VDD – 1.25 1.9 0.93 V VPP VPP 50 Ω to VDD – 2.0 V LVDS Output Option mid-level swing (diff) 1.125 0.32 1.2 0.40 1.275 0.50 V VPP Rterm = 100 Ω (differential) CML Output Option mid-level swing — 0.70 VDD – 0.75 0.95 — 1.20 V VPP Rterm = 100 Ω (differential) |
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