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PI74SSTU32864 Datasheet(PDF) 6 Page - Pericom Semiconductor Corporation |
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PI74SSTU32864 Datasheet(HTML) 6 Page - Pericom Semiconductor Corporation |
6 / 10 page 6 PS8636B 07/26/04 PI74SSTU32864 25-Bit 1:1 or 14-Bit 1:2 Configurable Buffer Notes 1. This parameter is not necessarily production tested. 2. Data and VREF inputs must be a low minimum time of tact max, after RST is taken high. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max after RST is taken low. Timing Requirements Over Recommended Operating Free Air Temperature range (See Figure 1) Parameter Description Min. Max Units fclock Clock frequency 270 MHz tW Pulse Duration, CK, CK, High or low 1 ns tact(1) Differential inputs active time(1) 10 tinact(1) Differential inputs inactive time(2) 15 tsu Setup time DCS before CK↑, CK↓, CSR high 0.7 DCS before CK↑, CK↓, CSR low 0.5 CSR DODT, CKE anddata before CK↑, CK↓ 0.5 th Hold Time DCS, CSR DODT, CKE adn data before CK↑, CK↓ 0.5 Notes: 1. The vendor must supply this value for full device description. Electrical Characteristics Over Recommended Operating Free Air Temperature range Parameters Description Test Conditions VDD Min. Nom. Max. Units VOH IOH = -6 mA 1.7V 1.2 V VOL IOL = 6 mA 1.7V 0.5 II All inputs VI = VDD or GND ±5 µA IDD Static Stand-by RST = GND IO = 0 1.9V 100 Static Operating RST = VDD, VI = VIH(AC) or VIL(AC) 40 mA IDDD Dynamic Operating Clock only RST = VDD, VI = VIH(AC), or VIL(AC) CK and CK switching 50% duty cycle 1.8V 28 µA/ clock MHz Dynamic Operating - per each data input, 1:1 mode RST = VDD, VI = VIH(AC), or VIL(AC) CK and CK switching 50% duty cycle. One data input switch- ing at half clock frequency, 50% duty cycle 18 µA/ clock MHz data input Dynamic Operating - per each data input, 1:2 mode RST = VDD, VI = VIH(AC), or VIL(AC) CK and CK switching 50% duty cycle. One data input switch- ing at half clock frequency, 50% duty cycle 36 CI Data inputsp VI = VREF ±250mV 2.5 3.5 pF CK and CK VICR = 0.9V, VID = 600mV 2 3 RST VI = VDD or GND 2.5 |
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