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HT46R48E Datasheet(PDF) 14 Page - Holtek Semiconductor Inc |
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HT46R48E Datasheet(HTML) 14 Page - Holtek Semiconductor Inc |
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14 / 46 page  HT46R48E Rev. 1.10 14 March 24, 2006 The registers ¢ states are summarized in the following table. Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Times-out (HALT)* TMR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu Program Counter 000H 000H 000H 000H 000H MP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu PCC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu PD ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u PDC ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u PWM xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRL x--- ---- x--- ---- x--- ---- x--- ---- u--- ---- ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu ACSR 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu Note: ²*² stands for warm reset ²u² stands for unchanged ²x² stands for unknown Timer/Event Counter A timer/event counter (TMR) is implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or the system clock. Using external clock input allows the user to count exter- nal events, measure time internals or pulse widths, or generate an accurate time base. While using the inter- nal clock allows the user to generate an accurate time base. The timer/event counter can generate PFD signal by us- ing external or internal clock and PFD frequency is de- termine by the equation fINT/[2 ´(256-N)]. There are 2 registers related to the timer/event counter; TMR ([0DH]), TMRC ([0EH]). Two physical registers are mapped to TMR location; writing TMR makes the start- ing value be placed in the timer/event counter preload register and reading TMR retrieves the contents of the timer/event counter. The TMRC is a timer/event counter control register, which defines some options. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the fINT clock. The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the fINT. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current con- tents in the timer/event counter to FFH. Once overflow oc- curs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request flag (TF; bit 5 of INTC) at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bits is ²0²) it will start counting until the TMR returns to the orig- inal level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle |
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