3

P/N:PM0716

REV. 1.7, JUN. 29, 2005

MX23L3213

AC Test Conditions

Input Pulse Levels

0V~ 3.0V

Input Rise and Fall Times

5ns

Input Timing Level

1.5V

Output Timing Level

1.5V

Output Load

See Figure

Note:No output loading is present in tester load board.

Active loading is used and under software programming control.

Output loading capacitance includes load board's and all stray capacitance.

DOUT

C<100pF

IOL (load)=1.6mA

IOH (load)=-0.4mA

TIMING DIAGRAM

RANDOM READ

Note:

30pF output load capacitance for 70 and 90ns

speed grade

100pF output load capacitance for 120ns speed

grade

tACE

tAA

tOH

tHZ

ADD

ADD

ADD

ADD

CE#

OE#

DATA

VALID

VALID

VALID

tRC

tOE

AC CHARACTERISTICS (Ta = -40

° C ~ 85° C, VCC = 2.7V~3.6V)

Item

Symbol

23L3213-70

23L3213-90

23L3213-10

23L3213-12

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Read Cycle Time

tRC

70ns

-

90ns

-

100ns

-

120ns

-

Address Access Time

tAA

-

70ns

-

90ns

-

100ns

-

120ns

Chip Enable Access Time

tACE

-

70ns

-

90ns

-

100ns

-

120ns

Output Enable Time

tOE

-

30ns

-

40ns

-

40ns

-

50ns

Output Hold After Address

tOH

0ns

-

0ns

-

0ns

-

0ns

-

Output High Z Delay

tHZ

-

20ns

-

20ns

-

20ns

-

20ns

Note:Output high-impedance delay (tHZ) is measured from OE# or CE# going high, and this parameter guaranteed

by design over the full voltage and temperature operating range - not tested.