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TTSI008321BL-2-DB Datasheet(PDF) 8 Page - Agere Systems |
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TTSI008321BL-2-DB Datasheet(HTML) 8 Page - Agere Systems |
8 / 25 page TSI-8 Hardware Design Guide, Revision 1 8K x 8K Time-Slot Interchanger November 2, 2005 8 8 Agere Systems Inc. 3.3 Ball Types This table describes each type of input, output, and I/O ball used on the TSI-8. The dc switching and other electrical characteristics are specified later in this document. 3.4 Ball Definitions This section describes the function of each of the device balls. The balls are listed by ball name. Package ball numbers are listed in Table 3-1 of this document. The static parameters (drive currents, switching thresholds, etc.) for each ball type (in- put, output, etc.) are described in Table 5-1 through Table 5-4. Table 3-4. Ball Types Type Label Description I CMOS input, TTL switching thresholds. I pd CMOS input, TTL switching thresholds with internal pull-down resistor. I pu CMOS input, TTL switching thresholds with internal pull-up resistor. O CMOS output. O od Open drain output. I/O Bidirectional ball; CMOS input with TTL switching thresholds and CMOS output. None Analog inputs for external resistors, capacitors, voltage references, etc. P Power and ground. Table 3-5. Timing Port Ball Name Type Name/Description FSYNC I Frame Synchronization. This signal indicates the beginning of a 125 µs frame event (8 kHz). The FSYNC ball can be programmed as active-low or active-high, but its polarity is the same for all concen- tration highway interfaces (CHI). FSYNC can be sampled on either the positive or negative edge of CHICLK. Time-slot numbers and bit offsets for each CHI are assigned relative to the detection of FSYNC. CHICLK I Clock. This is the master synchronous clock for the transmit and receive concentration highways. The frequency can be 8.192 MHz or 16.384 MHz. It must be at least as fast as the highest CHI data rate. CKSPD0 I Clock Speed. Static control input that should be tied according to the frequency of CHICLK. If CHICLK is connected to an 8.192 MHz source, CKSPD0 should be tied to VSS. If CHICLK is connected to a 16.384 MHz source, CKSPD0 should be tied to VDD33. CKSPD1 I pd Clock Speed. Reserved, leave disconnected. 20 k Ω pull-down resistor. Table 3-6. Transmit and Receive Concentration Highways Ball Name Type Name/Description RXD[31:00] I pd Receive Data [31:00]. Receive concentration highways. These are serial, synchronous data streams which may be individually programmed to operate at 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s. They carry 32, 64, 128, or 256 time slots (respectively) each occupying eight contiguous bits. 20 k Ω pull-down resistor. TXD[31:00] I/O Transmit Data [31:00]. Normally these are output concentration highway data streams with data rate options identical to the RXD inputs. These balls can be configured to operate as bidirectional multiplex ports such as H.110. Further information can be found in the system design guide. 20 k Ω resistor connected to VPRE. |
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