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TSOT0410G4 Datasheet(PDF) 6 Page - Agere Systems |
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TSOT0410G4 Datasheet(HTML) 6 Page - Agere Systems |
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6 / 190 page  List of Tables Contents Page 6 Agere Systems Inc. Data Sheet May 2003 STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order....................................................................... 17 Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order ..................................................................... 22 Table 3. Pin Descriptions—System Control ........................................................................................................... 26 Table 4. Pin Descriptions—Receive Line Interface ................................................................................................ 27 Table 5. Pin Descriptions—Transmit Line Interface ............................................................................................... 28 Table 6. Pin Descriptions—LVDS Reference, Line Interface ................................................................................. 30 Table 7. Pin Descriptions—Receive Drop Equipment Interface ............................................................................. 31 Table 8. Pin Descriptions—Transmit Add Equipment Interface ............................................................................. 33 Table 9. Pin Descriptions—LVDS Reference, Equipment Interface....................................................................... 35 Table 10. Pin Descriptions—Transport Overhead Interface................................................................................... 36 Table 11. Pin Descriptions—Microprocessor Interface .......................................................................................... 42 Table 12. Pin Descriptions—JTAG Interface.......................................................................................................... 43 Table 13. Pin Descriptions—PLL References ........................................................................................................ 44 Table 14. Pin Descriptions—Power and Ground.................................................................................................... 44 Table 15. Pin Summary .......................................................................................................................................... 46 Table 16. LOS Detector Register Summary ........................................................................................................... 48 Table 17. Framer Register Summary ..................................................................................................................... 50 Table 18. Descrambler Register Summary ............................................................................................................ 50 Table 19. STS-192 Byte Ordering .......................................................................................................................... 51 Table 20. STS-48 Byte Ordering ............................................................................................................................ 51 Table 21. Receive Overhead Serial Links Register Summary ............................................................................... 52 Table 22. J0 Register Summary ............................................................................................................................. 54 Table 23. B1 Register Summary ............................................................................................................................ 55 Table 24. BER Threshold Time and Error Limits for Line SD and SF Detection .................................................... 56 Table 25. B2 Register Summary ............................................................................................................................ 58 Table 26. APS Channel (K1 and K2) Register Summary ....................................................................................... 59 Table 27. Synchronization Status (S1) Register Summary .................................................................................... 61 Table 28. Line REI (M1) Register Summary........................................................................................................... 61 Table 29. STS-12 Byte Ordering ............................................................................................................................ 62 Table 30. Pointer Interpreter Register Summary.................................................................................................... 64 Table 31. Elastic Store Register Summary............................................................................................................. 65 Table 32. Pointer Generator Bypass Register Summary ....................................................................................... 65 Table 33. AIS-P Insertion Conditions ..................................................................................................................... 66 Table 34. Path AIS Insertion Register Summary.................................................................................................... 67 Table 35. Concatenation Register Summary.......................................................................................................... 68 Table 36. Pointer Justification Binning Register Summary..................................................................................... 68 Table 37. J1 Register Summary ............................................................................................................................. 70 Table 38. BER Threshold Time Window and Error Limits for Path SF Detection................................................... 71 Table 39. Time Window Sizes for Path SF Detection............................................................................................. 71 Table 40. B3 Register Summary ............................................................................................................................ 72 Table 41. STS Path Signal Label Assignments...................................................................................................... 73 Table 42. Path Signal Label (C2) Alarm Scenarios ................................................................................................ 74 Table 43. C2 Register Summary ............................................................................................................................ 75 Table 44. RDI-P Codes and Interpretation ............................................................................................................. 76 Table 45. G1 Register Summary ............................................................................................................................ 76 Table 46. Path Alarm Information Encoding........................................................................................................... 77 Table 47. Line Alarm Information Encoding ........................................................................................................... 78 Table 48. Drop Interface Overhead and Scrambling Register Summary ...............................................................78 Table 49. Timing Enable Bit Definitions.................................................................................................................. 79 Table 50. Receive Data Path Parity Register Summary......................................................................................... 79 Table 51. LTE Transmit Channel Registers—Regenerator Loopback Summary................................................... 80 |
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