Product Description, Revision 4

TFRA84J13 Ultraframer

April 29, 2005

DS3/E3/DS2/E2/DS1/E1/DS0

Agere Systems Inc.

11

5.2 Multirate Cross Connect (MRXC)

The multirate cross connect (MRXC) functional block (one

per device) is a crosspoint switch for DS1/J1/E1/DS2/E2

and DS3/E3 signals. The multirate cross connect routes

signals to/from the major functional blocks and external I/O

pins as necessary for each application. The MRXC can

multicast, route test patterns, idles, or alarm conditions to

any channel, and provide system loopbacks.

For DS1/E1 applications, the multirate cross connect can

interconnect up to 84 individual DS1/E1 channels between

the framer, M13/E13 multiplexer, jitter attenuator, or exter-

nal I/O. The external I/O pins support an application-depen-

dent mix of up to 86 DS1/E1* interfaces (allowing for

dedicated protection channels or additional DS1/E1 chan-

nels), 21 DS2 interfaces, or one of four available system

interfaces.

Independent signal paths for remote alarm indication (RAI)

and alarm indication signal (AIS) on channels between the

M13/E13 and the framer are supported.

The multirate cross connect has independent DS2 inter-

faces for the M12 and M23 subblocks of the M13 MUX. Full

split access to the external I/O device pins provides the

capability to add, drop, or rearrange the DS2 signals within

the M13.

The test-pattern generator/monitor functional block (TPG/

TPM) provides test signals and monitors inputs for signals

to/from the multirate cross connect. The TPG can generate

a set of test signals at DS1, E1, and DS2. There is only one

test pattern generator and monitor per signal rate.

The MRXC also provides the interface to the external pins.

The external pins may be configured to work in four modes:

a transport mode, a concentration highway interface (CHI)

mode, a parallel system bus (PSB) mode, and a network

serial multiplexed interface (NSMI) mode. The first mode is

used to provide dedicated access to the device for DS3/E3/

DS2/E2/DS1/E1 signals, and the last three modes are

described below.

Concentration highway interface (serial time-division

multiplex interface) CHI:

— Global frame synchronization.

— Global clock: 8.192 MHz or 16.384 MHz.

— 18 transmit and 18 receive data ports; data rates:

8.192 Mbits/s or 16.384 Mbits/s.

Parallel system bus (parallel time-division multiplex inter-

face/transmit and receive) PSB:

— Global frame synchronization.

— Global clock: 19.44 MHz.

— Data rate: 19.44 Mbits/s.

— 8 bits of data + associated parity bit.

— 4 bits of signaling + 2 bits of signaling control + 1 bit of

parity.

* The 85th and 86th DS1 I/O may only be used for protection channels

with applications in which the other 84 I/O are fixed (see MRXC section

of the Register Description for more information). Otherwise, applica-

tions are practically limited to 84 I/O.

Network serial multiplexed bus (NSMI):

— Framer—NSMI payload assembled/disassembled into

DS1/E1s.

— 6-pin or 8-pin serial interface.

— Transmit and receive clock and data at 51.84 MHz.

— Provides a minimal pin count interface for data and

inverse multiplexing for ATM (IMA) applications with-

out slip

buffers.

5.3 DS1 Digital Jitter Attenuator (DS1/E1 DJA)

The DS1/E1 digital jitter attenuator (DS1/E1 DJA) block

(three per device), contains 28 copies of the digital jitter

attenuator for a total of 84/63 DS1/E1 DJAs. These digital

jitter attenuator functional blocks can operate in two differ-

ent modes: as a DS1 or as an E1 jitter attenuator.

In both modes, the digital jitter attenuator can be provi-

sioned to always operate as a second-order PLL, or it can

switch to act as a first-order PLL during VT pointer adjust-

ments to help meet MTIE requirements. The period of time

in the first-order mode is provisionable. The PLL bandwidth

is provisionable between 0.1 Hz and 0.5 Hz, and the damp-

ing factor for these bandwidths varies between 2 and 0.5 to

accommodate a number of different system constraints.

The DS1/E1 DJA allows automatic pass-through of an AIS

from M13/E13 blocks.

5.4 Test Pattern Generator/Monitor (TPG/TPM)

The test pattern generator/test pattern monitor functional

block (TPG/TPM) consists of a set of configurable test pat-

tern generators and monitors for local self-test, mainte-

nance, and troubleshooting operations.

The TPG feeds one or more DS1/E1/DS2 test signals (via

data, clock, and FS (DS1/E1 only) or AIS signal paths) to

the multirate cross connect, which can redistribute or

broadcast these signals to any valid channel in the framer,

external I/O, or M13/E13 MUX.

Any channel arriving at the multirate cross connect can be

routed to the test monitor. The test monitor can automati-

cally detect/count bit errors in a pseudorandom test

sequence, loss of frame (DS1/E1 only), or loss of synchro-

nization situation. The TPM can provide an interrupt to the

control system, or it can be operated in a polled mode.

Simultaneous testing of DS1, E1, and DS2 signals is sup-

ported with one channel for each.

Supported test patterns are a quasirandom signal (QRSS),

a pseudorandom bit sequence (PRBS23, PRBS20,

PRBS15), alternating zeros/ones, an all-ones pattern, and

a 16-bit user-provisionable pattern.