Advance Data Sheet

March 26, 2004

LCK4972 Low-Voltage PLL Clock Driver

Agere Systems Inc.

5

Table 3-1. Pin Description

Pin

Symbol

Type

Description

1, 15, 24, 30,

35, 39, 47, 51

Ground

—

Ground.

2

MROEB

LVTTL

Master Reset and Output Enable Input.

0 = Outputs disabled (high-impedance state). During this condition the PLL

loop is open and the VCO will run at an indeterminate frequency.

1 = Normal operation (outputs active).

3

Frz_Clk

LVTTL

I

Freeze Mode.

4

Frz_Data

LVTTL

I

Freeze Mode.

5

fselFB2

LVTTL

Feedback Output Divider Function Select. This input, along with pins

fselFB0 and fselFB1, controls the divider function of the feedback bank of

outputs. See Table 4-2 for more details.

6

PLL_EN

LVTTL

PLL Bypass Select.

0 = The internal PLL is bypassed and the selected reference input provides

the clocks to operate the device.

1 = The internal PLL provides the internal clocks to operate the device.

7

Ref_Sel

LVTTL

Reference Select Input. The Ref_Sel input controls the reference input to

the PLL.

0 = The input is selected by the TCLK_Sel input.

1 = The XTAL is selected.

8

TCLK_Sel

LVTTL

TCLK Select Input. The TCLK_Sel input controls which TCLK input will be

used as the reference input if Ref_Sel is set to 0.

0 = TCLK0 is selected.

1 = TCLK1 is selected.

9, 10

TCLK[0:1]

LVTTL

I

LVTLL Reference Input. These inputs provide the reference frequency for

the internal PLL when selected by Ref_Sel and TCLK_Sel.

11

xtal1

Analog

I

Xtal Reference Input. This input provides the reference frequency for the

internal PLL when selected by Ref_Sel.

12

xtal2

Analog

I

Xtal Reference Input. This input provides the reference frequency for the

internal PLL when selected by Ref_Sel.

13

Power

—

PLL Power.

14

Inv_Clk

LVTTL

Invert Mode. This input only affects the Qc bank.

0 = All outputs of the Qc bank are in the normal phase alignment.

1 = Qc2 and Qc3 are inverted from the normal phase of Qc0 and Qc1.

16, 18, 21, 23

Qc[3:0]

LVTTL

O

Clock Output. These outputs, along with the Qa[0:3], Qb[0:3], and QFB

outputs, provide numerous divide functions determined by the fsela[0:3],

fselb[0:3], and the fselFB[0:2] See Table 4-1 and Table 4-2 for more details.

17, 22, 33,

37, 45, 49

Power

—

Output Buffer Power.

19, 20

fselc[1:0]

LVTTL

Output Divider Function Select. Each pair controls the divider function of

the respective bank of outputs. See Table 4-1 for more details.

* U = Internal pull-up resistors (50 k

Ω).