Advance Data Sheet

LCK4972 Low-Voltage PLL Clock Driver

March 26, 2004

10

10

Agere Systems Inc.

The Inv_Clk input pin, when asserted, will invert the Qc2 and Qc3 outputs. This inversion does not affect the output-output

skew of the device and allows for the development of 180° phase-shifted clocks. This output can also be used as a feedback

output or routed to a second PLL to generate early/late clocks. Figure 4-5 shows a 90° phase-shift configuration.

2337 (F)

Figure 4-5. Phase Delay Example Using Two LCK4972s

4.4 SYNC Output

When the output frequencies are not integer multiples of each other, there is a need for a signal for synchronization purpos-

es. The SYNC output is designed to address this need. The Qa and Qc banks of outputs are monitored by the device, and

a low-going pulse (one period in duration, one period before the coincident rising edges of Qa and Qc) is provided. The du-

ration and placement of the pulse is dependent on the highest of Qa and Qc output frequencies. The timing diagram,

(Figure 4-6) shows the various waveforms for SYNC.

Note: SYNC is defined for all possible combinations of Qa and Qc, even though the lower frequency clock should be used

as a synchronizing signal in most cases.

fsela0

fsela1

fselb0

fselb1

fselc0

fselc1

fselFB0

fselFB1

fselFB2

0

0

0

0

1

0

0

0

0

LCK4972

Qa

Qb

Qc

Qc

66 MHz

66 MHz

66 MHz

66 MHz

4

4

2

66 MHz

Input Ref

Ext_FB

Inv_Clk

1

fsela0

fsela1

fselb0

fselb1

fselc0

fselc1

fselFB0

fselFB1

fselFB2

0

1

0

1

1

1

0

0

0

LCK4972

Qa

Qb

Qc

QFB

33 MHz SHIFTED 90°

33 MHz SHIFTED 90°

33 MHz SHIFTED 90°

66 MHz

4

4

4

Input Ref

Ext_FB

Inv_Clk

0

QFB

66 MHz

66 MHz

33 MHz

SHIFTED 90°

2