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LCK4310GF-DB Datasheet(PDF) 3 Page - Agere Systems |
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LCK4310GF-DB Datasheet(HTML) 3 Page - Agere Systems |
3 / 10 page Data Sheet LCK4310 April 20, 2004 Low-Voltage PLL Clock Driver Agere Systems Inc. 3 3.2 Pin Descriptions Table 3-1. Pin Descriptions 3.3 Logic Symbol Figure 3-2. Logic Symbol Pin Symbol Type I/O Description 1VDD Power — Positive Power Supply. 2 CLKa PECL I ECL Differential Input Clock. Makes input pair with CLKa. 3VBB VREFOUT O Reference Voltage Output. 4 CLKb PECL I ECL Differential Input Clock. Makes input pair with CLKb. 5 CLKb PECL I ECL Differential Input Clock. Makes input pair with CLKb. 6 NC —— No Connect. 7, 10, 12, 14, 17, 19, 21, 24 Q[7:0] PECL O ECL Differential Outputs. 8, 15, 22 VDDO Power — Positive Power Supply. 9, 11, 13, 16, 18, 20, 23, 25 Q[7:0] PECL O ECL Differential Outputs. 26 VEE Power — Negative Power Supply. 27 CLK_SEL LVTTL I ECL Input Clock Select. 0 = CLKa selected. 1 = CLKb selected. 28 CLKa PECL I ECL Differential Input Clock. Makes input pair with CLKa. Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VBB Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 CLKa CLKa CLKb CLKb CLK_SEL CLK_SEL Input Clock L CLKa/CLKa Selected H CLKb/CLKb Selected |
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