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FW322061394 Datasheet(PDF) 6 Page - Agere Systems |
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FW322061394 Datasheet(HTML) 6 Page - Agere Systems |
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6 / 92 page  6 6 Agere Systems Inc. FW322 06 1394a Data Sheet, Rev. 1 PCI PHY/Link Open Host Controller Interface December 2005 Features (continued) PCI: — Revision 2.2 compliant — 33 MHz/32-bit operation — Programmable burst size thresholds for PCI data transfer — Supports optimized memory read line, memory read multiple, and memory write invalidate burst commands — Supports PCI Bus Power Management Interface Specification v.1.1, including D3cold wakeups — Supports CLKRUN# protocol per PCI Mobile Design Guide — Supports Mini PCI Specification v1.0, including Mini PCI power requirements — Global byte swap function — CardBus support per PC Card Standard Release 8.0, including 128 bytes of on-chip tuple memory Other Features I2C serial ROM interface CMOS process 3.3 V operation, 5 V tolerant inputs 120-pin TQFP package NAND tree test mode FW322 Functional Overview The FW322 is a high-performance, PCI bus-based open host controller designed by Agere Systems Inc. for imple- mentation of 1394a-2000 compliant systems and devices. Link-layer functions are handled by the FW322, utilizing the on-chip 1394a-2000 compliant link core and physical layer core. A high-performance and cost-effective solution for connecting and servicing multiple 1394 (both 1394-1995 and 1394a-2000) peripheral devices can be realized using this PHY/link OHCI device. 5-6250 (F).f Figure 1. FW322 Conceptual Block Diagram FW322 Functional Description The FW322 is comprised of four major functional sections (see Figure 1): PCI core, OHCI isochronous and asynchronous data transfer, link core, and PHY core. The following is a general description of each of the major sections. PCI BUS PCI ROM OHCI OHCI LINK CORE DATA DATA I/F CORE CABLE PORT 1 CABLE PORT 0 TRANSFER TRANSFER ASYNCHRONOUS ISOCHRONOUS CORE PHY |
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