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MXD2020G Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part No. MXD2020G
Description  Improved, Ultra Low Noise ±1.7 g Dual Axis Accelerometer with Digital Outputs
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Maker  ETC1 [List of Unclassifed Manufacturers]
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MXD2020G Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers

   
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MEMSIC MXD2020G/M/N/H Rev.E
Page 5 of 7
3/25/2005
Resolution: The accelerometer resolution is limited by
noise. The output noise will vary with the measurement
bandwidth. With the reduction of the bandwidth, by
applying an external low pass filter, the output noise drops.
Reduction of bandwidth will improve the signal to noise
ratio and the resolution. The output noise scales directly
with the square root of the measurement bandwidth. The
maximum amplitude of the noise, its peak- to- peak value,
approximately defines the worst case resolution of the
measurement. With a simple RC low pass filter, the rms
noise is calculated as follows:
Noise (mg rms) = Noise(mg/ Hz ) *
)
6
.
1
*
)
(
(
Hz
Bandwidth
The peak-to-peak noise is approximately equal to 6.6 times
the rms value (for an average uncertainty of 0.1%).
DIGITAL INTERFACE
The MXD2020G/H/M/N is easily interfaced with low cost
microcontrollers. For the digital output accelerometer, one
digital input port is required to read one accelerometer
output. For the analog output accelerometer, many low cost
microcontrollers are available today that feature integrated
A/D (analog to digital converters) with resolutions ranging
from 8 to 12 bits.
In many applications the microcontroller provides an
effective approach for the temperature compensation of the
sensitivity and the zero g offset. Specific code set, reference
designs, and applications notes are available from the
factory. The following parameters must be considered in a
digital interface:
Resolution: smallest detectable change in input acceleration
Bandwidth: detectable accelerations in a given period of
time
Acquisition Time: the duration of the measurement of the
acceleration signal
DUTY CYCLE DEFINITION
The MXD2020G/H/M/N has two PWM duty cycle outputs
(x,y). The acceleration is proportional to the ratio T1/T2.
The zero g output is set to 50% duty cycle and the
sensitivity scale factor is set to 20% duty cycle change per
g. These nominal values are affected by the initial
tolerance of the device including zero g offset error and
sensitivity error. This device is offered from the factory
programmed to either a 10ms period (100 Hz) or a 2.5ms
period (400Hz).
T1
Length of the “on” portion of the cycle.
T2 (Period)
Length of the total cycle.
Duty Cycle
Ratio of the “0n” time (T1) of the cycle to
the total cycle (T2). Defined as T1/T2.
Pulse width
Time period of the “on” pulse. Defined as
T1.
T2
T1
A (g)= (T1/T2 - 0.5)/20%
0g = 50% Duty Cycle
T2= 2.5ms or 10ms (factory programmable)
Figure 2: Typical output Duty C ycle
CHOOSING T2 AND COUNTER FREQUENCY
DESIGN TRADE-OFFS
The noise level is one determinant of accelerometer
resolution. The second relates to the measurement
resolution of the counter when decoding the duty cycle
output. The actual resolution of the acceleration signal is
limited by the time resolution of the counting devices used
to decode the duty cycle. The faster the counter clock, the
higher the resolution of the duty cycle and the shorter the
T2 period can be for a given resolution. Table 2 shows
some of the trade-offs. It is important to note that this is the
resolution due to the microprocessors’ counter. It is
probable that the accelerometer’s noise floor may set the
lower limit on the resolution.
T2 (ms)
MEMSIC
Sample
Rate
Counter-
Clock
Rate
(MHz)
Counts
Per T2
Cycle
Counts
per g
Reso-
lution
(mg)
2.5
400
2.0
5000
1000
1.0
2.5
400
1.0
2500
500
2.0
2.5
400
0.5
1250
250
4.0
10.0
100
2.0
20000
4000
0.25
10.0
100
1.0
10000
2000
0.5
10.0
100
0.5
5000
1000
1.0
Table 2: Trade-Offs Between Microcontroller Counter Rate and
T2 Period.
CONVERTING THE DIGITAL OUTPUT TO AN
ANALOG OUTPUT
The PWM output can be easily converted into an analog
output by integration. A simple RC filter can do the
conversion. Note that that the impedance of the circuit
following the integrator must be much higher than the
impedance of the RC filter. Reference figure 3 for an
example.


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