ADSY8401

Rev. 0 | Page 7 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADSY8401

TOP VIEW

(Not to Scale)

DVCC

1

GSW

2

SEL

3

AGNDL

4

DO9T

5

DO9C

6

DO10T

7

DO10C

8

DO11T

9

AVCCL3

36

DO1

35

DO2

34

DO3

33

DO4

32

AGNDL

31

AVCCL2

30

DO5

29

DO6

28

DO7

27

DO8

26

AGNDL

25

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 18

DVCC

Digital Power Supply.

2

GSW

Grounded Mode Switch. When the voltage on the GSW pin is tied to DGND, the AMPO, MUXO, and

BFRO outputs are pulled to near AGND. When the GSW input is left unconnected or tied to DVCC, all

outputs operate normally. The level shifters are not affected by the GSW input.

3, 39–41

SEL, MUXA, MUXB,

MUXO

Analog Precharge. Low offset unity gain amplifier with MUXed inputs. Drives large capacitive loads. For

driving large capacitive loads at high slew rates, connect MUXO to BFRI and the load capacitance to

BFRO.

SEL = HIGH selects MUXA.

4, 25, 31

AGNDL

Level Shifter Ground.

5–10

DO9–11T, DO9–11C

Complementary Level Shifter Outputs. While the corresponding input voltage of these level shifters is

11, 30, 36

AVCCL1, 2, 3

Level Shifter Power Supply.

12–14

DI9–11

Complementary Level Shifter Inputs. Low voltage input of the complementary level shifters.

15–17,

20–24

DI1–8

Inverting Level Shifter Inputs. Low voltage input of the inverting level shifters.

19, 47

DGND

Digital Ground. This pin is normally connected to the digital ground plane.

26–29,

32–35

DO1-8

Inverting Level Shifter Outputs. While the corresponding input voltage of these level shifters is below

37–38

AMPO, AMPI

Analog Amplifier. Low offset unity gain amplifier. Drives large capacitive loads such as VCOM.

42, 44

BFRI, BFRO

Analog Buffer. High current output buffer.

43

AVCC

Analog Power Supplies. Analog power supplies for the level shifter and the amplifiers.

45

AGND

Analog Supply Returns. Analog supply returns for the level shifter and the amplifiers.

46

DTCTO

Edge Detecting Level Shifter Output. Logic output of the inverting level shifting edge detector.

48

DTCTI

Edge Detecting Level Shifter Input. High voltage input of the inverting level shifting edge detector.