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APPLICATION INFORMATION

SYSTEM-1

SYSTEM-2

1

2

3

4

8

7

6

5

DIR CTRL

I/O-1

I/O-2

Enable Times

SN74AVCH2T45

DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER

WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SCES582D – JULY 2004 – REVISED AUGUST 2005

Figure 13 shows the SN74AVCH2T45 used in a bidirectional logic level-shifting application. Since the

SN74AVCH2T45 does not have an output-enable (OE) pin, system designers should take precautions to avoid

bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.

Figure 13. Bidirectional Logic Level-Shifting Application

Following is a sequence that shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2

to SYSTEM-1.

STATE

DIR CTRL

I/O-1

I/O-2

DESCRIPTION

1

H

Out

In

SYSTEM-1 data to SYSTEM-2

SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2

2

H

Hi-Z

Hi-Z

are disabled.

The bus-line state depends on bus hold.

DIR bit is flipped. I/O-1 and I/O-2 still are disabled.

3

L

Hi-Z

Hi-Z

The bus-line state depends on bus hold.

4

L

Out

In

SYSTEM-2 data to SYSTEM-1

Calculate the enable times for the SN74AVCH2T45 using the following formulas:

•

•

•

•

In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is

switched until an output is expected. For example, if the SN74AVCH2T45 initially is transmitting from A to B, the

DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port

has been disabled, an input signal applied to it appears on the corresponding A port after the specified

propagation delay.

17