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XRT72L50IQ Datasheet(PDF) 7 Page - Exar Corporation |
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XRT72L50IQ Datasheet(HTML) 7 Page - Exar Corporation |
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7 / 471 page  áç áç áç áç XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. 1.2.1 V Figure 40. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 5 (Nibble- Parallel/Local-Timed/Frame-Slave) Operation ............................................................................................. 147 4.2.1.6 Mode 6 - The Nibble-Parallel/TxInClk/Frame-Master Interface Mode Behavior of the XRT72L50 148 Figure 41. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (DS3 Mode 5 Operation) .................................................................................................................................................... 148 Figure 42. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 6 (Nibble- Parallel/Local-Timed/Frame-Master) Operation ........................................................................................... 149 Figure 43. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (DS3 Mode 6 Operation) .................................................................................................................................................... 150 4.2.2 The Transmit Overhead Data Input Interface ........................................................................................ 151 Figure 44. The Transmit Overhead Data Input Interface block .................................................................................... 151 4.2.2.1 Method 1 - Using the TxOHClk Clock Signal .............................................................................. 152 TABLE 16: OVERHEAD BITS WITHIN THE DS3 FRAME AND THEIR POTENTIAL SOURCES WITHIN THE XRT72L50 IC ............. 152 TABLE 17: DESCRIPTION OF METHOD 1 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ............................................... 153 Figure 45. The Terminal Equipment being interfaced to the Transmit Overhead Data Input Interface (Method 1) ..... 154 TABLE 18: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN TXOHCLK SINCE TXOHFRAME WAS LAST SAMPLED "HIGH" TO THE DS3 OVERHEAD BIT THAT IS BEING PROCESSED ....................................................... 154 Figure 46. Illustration of the signal that must occur between the Terminal Equipment and the XRT72L50, in order to configure the XRT72L50 to transmit a Yellow Alarm to the remote terminal equipment ............................................. 157 4.2.2.2 Method 2 - Using the TxInClk and TxOHEnable Signals ............................................................ 158 TABLE 19: DESCRIPTION OF METHOD 2 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ............................................... 158 Figure 47. The Terminal Equipment being interfaced to the Transmit Overhead Data Input Interface (Method 2) ..... 159 TABLE 20: THE RELATIONSHIP BETWEEN THE NUMBER OF TXOHENABLE PULSES SINCE THE LAST OCCURRENCE OF THE TXOHFRAME PULSE, TO THE DS3 OVERHEAD BIT THAT IS BEING PROCESSED BY THE XRT72L50 ................... 159 4.2.3 The Transmit DS3 HDLC Controller ...................................................................................................... 162 4.2.3.1 Bit-Oriented Signaling (or FEAC Message) processing via the Transmit DS3 HDLC Controller. 162 Figure 48. Behavior of Transmit Overhead Data Input Interface signals between the XRT72L50 and the Terminal Equipment (for Method 2) .............................................................................................................................................. 162 4.2.3.2 Message-Oriented Signaling (e.g., LAP-D) processing via the Transmit DS3 HDLC Controller 164 Figure 49. A Flow Chart depicting how to transmit a FEAC Message via the FEAC Transmitter ............................... 164 Figure 50. LAPD Message Frame Format .................................................................................................................. 165 TABLE 21: THE LAPD MESSAGE TYPE AND THE CORRESPONDING VALUE OF THE FIRST BYTE WITHIN THE INFORMATION PAYLOAD 166 TABLE 22: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE ........................................... 166 TABLE 23: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE ........................................... 167 Figure 51. Flow Chart depict how to use the LAPD Transmitter ................................................................................. 169 4.2.4 The Transmit DS3 Framer Block ........................................................................................................... 170 4.2.4.1 Brief Description of the Transmit DS3 Framer ............................................................................ 170 4.2.4.2 Detailed Functional Description of the Transmit DS3 Framer Block ........................................... 171 Figure 52. The Transmit DS3 Framer Block and the associated paths to other Functional Blocks ............................. 172 TABLE 24: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 7 (TX YELLOW ALARM) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION ...................................................... 173 TABLE 25: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 6 (TX X-BITS) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION .............................................................................. 173 TABLE 26: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 5 (TX IDLE) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER ACTION ............................................................................................ 174 TABLE 27: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 4 (TX AIS PATTERN) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION ...................................................... 174 TABLE 28: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (TX LOS) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION .............................................................................. 175 4.2.5 The Transmit DS3 Line Interface Block ................................................................................................. 177 Figure 53. Interfacing the XRT72L50 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU .............................................. 178 Figure 54. The Transmit DS3 LIU Interface block ....................................................................................................... 178 4.2.5.1 Selecting the various Line Codes ............................................................................................... 179 Figure 55. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit DS3 LIU Interface is operating in the Unipolar Mode ................................................................................................................... 179 TABLE 29: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR) WITHIN THE UNI I/O CONTROL REGISTER AND THE TRANSMIT DS3 FRAMER LINE INTERFACE OUTPUT MODE .................................................................. 180 Figure 56. Illustration of AMI Line Code ..................................................................................................................... 180 4.2.5.2 TxLineClk Clock Edge Selection ................................................................................................. 181 Figure 57. Illustration of two examples of B3ZS Encoding ......................................................................................... 181 TABLE 30: THE RELATIONSHIP BETWEEN BIT 4 (AMI/B3ZS*) WITHIN THE I/O CONTROL REGISTER AND THE BIPOLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT DS3 LIU INTERFACE BLOCK ...................................................................... 181 TABLE 31: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE |
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