MVTX1100

Data Sheet

8

Zarlink Semiconductor Inc.

1.0

Functional Operation

The MVTX1100 was designed to provide a cost-effective layer 2 switching solution, using technology from the

Zarlink family to offer a highly integrated product for the unmanaged, DiffServ ready, Ethernet switching market.

Nine 1/10 Media Access Controllers (MAC) provide the protocol interface into the MVTX1100. These MACs perform

the required packet checks to ensure that each packet provided to the Frame Engine meets all the IEEE 802.1

standards. Data packets longer than 1518 (1522 with VLAN tag) bytes and shorter than 64 bytes are dropped and

MVTX1100 has been designed to support minimum inter-frame gaps between incoming packets.

The PHY addresses for the 8 RMII MACs are from 08h to 0Fh. These eight ports are denoted as ports 0 to 7. The

PHY address for the uplink MAC is 10h. This port is denoted as port 8.

The Frame Engine (FE) is the primary packet buffering and forwarding engine within the MVTX1100. As such, the

FE controls the storage of packets in and out of the external frame buffer memory, keeps track of frame buffer

availability and schedules output packet transmissions. While packet data is being buffered, the FE extracts the

necessary information from each packet header and sends it to the Search Engine for processing. Search results

returned to the FE ensue the scheduling of packet transmission and prioritization. When a packet is chosen for

transmission, the FE reads the packet from external buffer memory and places it in the output FIFO of the output

port.

2.0

Address Learning and Aging

The MVTX1100 is able to begin address learning and packet forwarding shortly after powerup has been completed.

The Search Engine examines the contents of its internal Switch Database Memory for each valid packet received

on an input port.

Unknown source and destination MAC addresses are detected when the Search Engine does not find a match

within its database. These unknown source MAC addresses are learned by creating a new entry in the switch

database memory, and storing the necessary resulting information in that location. Subsequent searches to a

learned destination MAC address will return the new contents of that MAC Control Table (MCT) entry.

After each source address search the MCT entry aging flag is updated. MCT entries that have not been accessed

during a user configurable time period (2 to 67,108 seconds) will be removed. This aging time period can be

configured using the 16-bit value stored in the registers MAC Address Aging Time Low and High (MATL[7:0],

MATH[7:0]). The aging period is defined by the following equation:

{MATH[7:0]&MATL[7:0]} x 1024ms = Tage

The aging of all MCT entries is checked once during each time period. If the MCT entry has not been utilized before

the end of the next time period, it will be deleted.

Note that when the system clock operates at 20 MHz, the aging period will be increased, compared with 50 MHz of

system clock. One should adjust the MATH and MATHL content variable accordingly.

3.0

Quality of Service

The MVTX1100 utilizes Zarlink’s architecture that provides a new level of (QoS) capability to unmanaged switch

applications. Similar in operation to the QoS capabilities of other Zarlink chipset members, MVTX1100 provides two

transmit queues per output port.

The Frame Engine manages the output transmission queues for all the MVTX1100 ports. Once the destination

address search is complete, and the switch decision is passed back to the FE, the packet is inserted into the

appropriate output queue. The packet entry into the high or low priority queue is controlled by either the VLAN tag

information or the Type of Service/Differentiated Service (TOS/DS) field in the IP header. Either of these priority

fields can be used to select the transmission priority, and the mapping of the priority field values into either the high

or low priority queue can be configured using the MVTX1100 configuration registers.