IS61C632A

Integrated Circuit Solution Inc.

1

SSR001-0B

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product.

We assume no responsibility for any errors

which may appear in this publication.

© Copyright 2000, Integrated Circuit Solution Inc.

FEATURES

•

Fast access time:

–

4 ns-125 MHZ; 5 ns-100 MHz;

6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz

•

Internal self-timed write cycle

•

Individual Byte Write Control and Global Write

•

Clock controlled, registered address, data and

control

•

Pentium™ or linear burst sequence control

using MODE input

•

Three chip enables for simple depth expansion

and address pipelining

•

Common data inputs and data outputs

•

Power-down control by ZZ input

•

JEDEC 100-Pin LQFP and PQFP package

•

Single +3.3V power supply

•

Two Clock enables and one Clock disable to

eliminate multiple bank bus contention.

•

Control pins mode upon power-up:

–

MODE in interleave burst mode

–

ZZ in normal operation mode

DESCRIPTION

The

ICSI

IS61C632A is a high-speed, low-power synchro-

nous static RAM designed to provide a burstable, high-perfor-

mance, secondary cache for the i486™, Pentium™, 680X0™,

and PowerPC™ microprocessors.

It is organized as 32,768

words by 32 bits, fabricated with

ICSI

's advanced CMOS

technology. The device integrates a 2-bit burst counter, high-

speed SRAM core, and high-drive capability outputs into a

single monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single clock

input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3

controls DQ17-DQ24,

BW4 controls DQ25-DQ32, conditioned

by

BWE being LOW. A LOW on GW input would cause all bytes

to be written.

Bursts can be initiated with either

ADSP (Address Status

Processor) or

ADSC (Address Status Cache Controller) input

pins. Subsequent burst addresses can be generated internally

by the IS61C632A and controlled by the

ADV (burst address

advance) input pin.

Asynchronous signals include output enable (

OE), sleep mode

input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH

input on the ZZ pin puts the SRAM in the power-down state.

When ZZ is pulled LOW (or no connect), the SRAM normally

operates after three cycles of the wake-up period. A LOW

(or no connect) on MODE pin selects INTERLEAVED Burst.

IS61C632A

32K x 32 SYNCHRONOUS PIPELINED STATIC RAM