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AL422 Datasheet(PDF) 14 Page - List of Unclassifed Manufacturers

Part No. AL422
Description  AL422 3M-Bits FIFO Field Memory
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Maker  ETC1 [List of Unclassifed Manufacturers]
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AL422 Datasheet(HTML) 14 Page - List of Unclassifed Manufacturers

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AL422
AL422B
January 23, 2001
14
memory does not accept data input. The write address pointer is stopped at the current position. /WE
signal is fetched at the rising edge of the WCK cycle.
/RE Read Enable Input: /RE controls the operation of the data output. When /RE is pulled low,
output data is provided at the rising edge of the RCK cycle and the internal read address is
incremented automatically. /RE signal is fetched at the rising edge of the RCK cycle.
/OE Output Enable Input: /OE controls the enabling/disabling of the data output. When /OE is
pulled low, output data is provided at the rising edge of the RCK cycle. When /OE is pulled high, data
output is disabled and the output pins remain at high impedance status.
/OE signal is fetched at the
rising edge of RCK cycle.
/WRST Write Reset Input: This reset signal initializes the write address to 0, and is fetched at the
rising edge of the WCK input cycle.
/RRST Write Reset Input: This reset signal initializes the read address to 0, and is fetched at the
rising edge of the RCK input cycle.
TST Test Pin: For testing purpose only. It should be pulled low for normal applications.
DEC: Decoupling cap pin, should be connected to a 1
µF or 2.2µF capacitor to ground for 5V
application. For 3.3V application, the DEC pin can be simply connected to the 3.3V power with
regular 0.1
µF bypass capacitor.
8.1 Memory Operation
Initialization
Apply /WRST and /RRST 0.1ms after power on, then follow the following instructions for normal
operation.
Reset Operation
The reset signal can be given at any time regardless of the /WE, /RE and /OE status, however, they
still need to meet the setup time and hold time requirements with reference to the clock input. When
the reset signal is provided during disabled cycles, the reset operation is not executed until cycles are
enabled again. When /WRST signal is pulled low, the data input address will be set to 0 and the data
in the Input Buffer will be flushed into memory cell array. When /RRST signal is pulled low, the data
output address will be set to 0 and pre-fetch the data from memory cell array to Output Buffer.


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