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TSC8051C2XXX16IAB Datasheet(PDF) 11 Page - TEMIC Semiconductors |
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TSC8051C2XXX16IAB Datasheet(HTML) 11 Page - TEMIC Semiconductors |
11 / 28 page TSC8051C2 Rev. A (10 Jan. 97) 11 Preview MATRA MHS 6.8.1. Interrupt Enable Register: Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register (IE SFR). All interrupts sources can also be globally enabled or disabled by setting or clearing the EA bit in IE register. IE: Interrupt Enable Register MSB SFR A8h LSB EA – – ES ET1 EX1 ET0 EX0 Symbol Position Name and Function EX0 IE.0 Enable external interrupt 0. ET0 IE.1 Enable timer 0 interrupt. EX1 IE.2 Enable external interrupt 1. ET1 IE.3 Enable timer 1 interrupt. ES IE.4 Enable UART interrupt. – IE.5 (Reserved). – IE.6 (Reserved). EA IE.7 Enable all interrupts. 6.8.2. Interrupt Priority Structure: Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are defined by the interrupt priority register (IP SFR). Setting a bit in the interrupt priority register selects a high priority interrupt, clearing it selects a low priority interrupt. IP: Interrupt Priority Register MSB SFR B8h LSB – – – PS PT1 PX1 PT0 PX0 Symbol Position Name and Function PX0 IP.0 External interrupt 0 priority level. PT0 IP.1 Timer 0 interrupt priority level. PX1 IP.2 External interrupt 1 priority level. PT1 IP.3 Timer 1 interrupt priority level. PS IP.4 UART interrupt priority level. – IP.5 (Reserved). – IP.6 (Reserved). – IP.7 (Unused). |
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