ICSLV810RILFT datasheet(7/12 Pages) ICST

Part #	ICSLV810RILFT

Description	Buffer/Clock Driver

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Manufacturer	ICST [Integrated Circuit Systems]

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Buffer/Clock Driver

MDS LV810 F

7

Revision 101305

Integrated Circuit Systems, Inc.

● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICSLV810

AC Electrical Characteristics—Bank B

VDDB = 2.5 V, Ambient Temperature -40

° C to +85° C, unless otherwise noted

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Output Skew: skew between

outputs of same package

tSK(0)CL = 3 pF, RL = 500

Ω

Figure 3

-200

200

ps

Pulse Skew: skew between

opposite transitions of same

output (tPLH-tPHL)

tSK(P)

CL = 3 pF, RL = 500

Ω

Figure 4

-200

200

ps

Propagation Delay

tpLH / tpHL

CL = 3 pF, RL = 500

Ω,

VDDB = 1.5 V

Figure 2

5.5

ns

CL = 3 pF, RL = 500

Ω,

VDDB = 2.5 V

Figure 2

1.5

2.6

3.5

ns

Part to Part Skew

CL = 3 pF, RL = 500

Ω

VDDB = 1.5 V

Figure 5

-1

1

ns

CL = 3 pF, RL = 500

Ω

VDDB = 2.5 V

Figure 5

-650

650

ps

Output Rise Time

20% to 80%

tr(o)

CL = 3 pF, RL = 500

Ω

VDDB = 1.5 V

1.0

ns

CL = 3 pF, RL = 500

Ω

VDDB = 2.5 V

0.8

ns

Output Fall Time

80% to 20%

tf(o)

CL = 3 pF, RL = 500

Ω

VDDB = 1.5 V

1.0

ns

CL = 3 pF, RL = 500

Ω

VDDB = 2.5 V

0.8

ns

Additive Jitter

tJ

All Outputs,

VDDB = 1.5 V

34

ps

All Outputs,

VDDB = 2.5 V

50

ps

Duty Cycle

Measured at VDD/2

DC

CL = 3 pF,

RL = 500

Ω

45

55

%

Duty Cycle, VDDB = 1.8V

DC

40

50

60

%

Output Frequency Range

1

133

MHz

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