Connection Diagram

20051803

Top View

See NS Package Number SLC64A

Truth Tables

Function Table for A to B Data Flow

Inputs

Outputs

OEAB

LEAB

CLKAB

A

B

LL

L

X

B

0 (Note 1)

LL

↑

LL

LL

↑

HH

LH

X

L

L

LH

X

H

H

H

XXX

Z

Function Table for B to A Data Flow

Inputs

Outputs

OEBA

LEBA

CLKBA

B

A

HL

L

X

A

0 (Note 1)

HL

↑

LL

HL

↑

HH

HH

X

L

L

HH

X

H

H

L

XXX

Z

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial (HIGH or LOW, inputs may not float)

Z = High Impedance

Note 1: Output level before the indicated steady-state input conditions were

established.

Functional Description

In the normal mode, these devices are 16-bit universal bus

transceivers that combine D-type latches and D-type flip-

flops to allow data flow in transparent, latched, or clocked

modes. They can be used as two 8-bit transceivers, or as

one 16-bit transceiver. The test circuitry can be activated by

the TAP to take snapshot samples of the data appearing at

the device pins or to perform a self test on the boundary-test

cells. Activating the TAP may affect the normal functional

operation of the universal bus transceivers. When the TAP is

activated, the test circuitry performs boundary-scan test op-

erations according to the protocol described in IEEE Std

1149.1-1990.

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the

devices operate in the transparent mode when LEAB is high.

When LEAB is low, the A data is latched while CLKAB is held

at a static low or high logic level. Otherwise, if LEAB is low,

A data is stored on a low-to-high transition of CLKAB. When

OEAB is LOW, the B outputs are active. When OEAB is

HIGH, the B outputs are in the high-impedance state. B-to-A

data flow is similar to A-to-B data flow but uses the OEBA,

LEBA, and CLKBA inputs. The output enables are compli-

mentary to facilitate the use of a single R/W signal without

additional logic.

Five dedicated test pins are used to observe and control the

operation of the test circuitry: test data input (TDI), test data

output (TDO), test mode select (TMS), test clock (TCK), and

test reset (TRST). All testing and scan operations are syn-

chronized to the TAP interface.

For details about the sequence of boundary scan cells in the

SCAN16602, please refer to the BSDL (Boundary Scan

Description Language) file available on our website at http://

www.national.com/scan.

www.national.com

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