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PIC10F206T Datasheet(PDF) 11 Page - Microchip Technology |
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PIC10F206T Datasheet(HTML) 11 Page - Microchip Technology |
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11 / 86 page  © 2005 Microchip Technology Inc. Preliminary DS41239B-page 9 PIC10F200/202/204/206 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC10F200/202/204/206 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC10F200/202/204/206 devices use a Harvard architecture in which program and data are accessed on separate buses. This improves band- width over traditional von Neumann architectures where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (1 μs @ 4 MHz) except for program branches. The table below lists program memory (Flash) and data memory (RAM) for the PIC10F200/202/204/206 devices. TABLE 3-1: PIC10F2XX MEMORY The PIC10F200/202/204/206 devices can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC10F200/202/ 204/206 devices have a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. This symmetrical nature and lack of “special optimal situations” make programming with the PIC10F200/202/204/206 devices simple, yet efficient. In addition, the learning curve is reduced significantly. The PIC10F200/202/204/206 devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8 bits wide and capable of addition, subtrac- tion, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two’s comple- ment in nature. In two-operand instructions, one oper- and is typically the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the Status register. The C and DC bits operate as a borrow and digit borrow out bit, respec- tively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1 and Figure 3-2, with the corresponding device pins described in Table 3-2. Device Memory Program Data PIC10F200 256 x 12 16 x 8 PIC10F202 512 x 12 24 x 8 PIC10F204 256 x 12 16 x 8 PIC10F206 512 x 12 24 x 8 |
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