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LTC3442EDE Datasheet(PDF) 8 Page - Linear Integrated Systems |
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LTC3442EDE Datasheet(HTML) 8 Page - Linear Integrated Systems |
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8 / 20 page  LTC3442 8 3442f The LTC3442 provides high efficiency, low noise power for applications such as portable instrumentation. The LTC proprietary topology allows input voltages above, below or equal to the output voltage by properly phasing the output switches. The error amp output voltage on VC determines the output duty cycle of the switches. Since VC is a filtered signal, it provides rejection of frequencies from well below the switching frequency. The low RDS(ON), low gate charge synchronous switches provide high frequency pulse width modulation control at high effi- ciency. Schottky diodes across the synchronous switch D and synchronous switch B are not required, but provide a lower voltage drop during the break-before-make time (typically 15ns). Schottky diodes will improve peak effi- ciency by typically 1% to 2%. High efficiency is achieved at light loads when Burst Mode operation is entered and the IC’s quiescent current drops to a low 35µA. LOW NOISE FIXED FREQUENCY OPERATION Oscillator The frequency of operation is programmed by an external resistor from RT to ground, according to the following equation: f R kHz Tk () () , = Ω 43 300 Error Amp The error amplifier is a voltage mode amplifier. The loop compensation components are configured around the amplifier (from FB to VC) to obtain stability of the con- verter. For improved bandwidth, an additional RC feed- forward network can be placed across the upper feedback divider resistor. The voltage on SHDN/SS clamps the error amp output, VC, to provide a soft-start function. OPERATIO Internal Current Limit There are three different current limit circuits in the LTC3442. Two have internally fixed thresholds which vary inversely with VIN, the third is externally programmable, and does not vary with input voltage. The first circuit is a high speed peak current limit amplifier that will shut off switch A if the current exceeds 5A typical. The delay to output of this amplifier is typically 50ns. A second amplifier will begin to source current into the FB pin to drop the output voltage once the peak input current exceeds 3A typical. This method provides a closed loop means of clamping the input current. During conditions where VOUT is near ground, such as during a short-circuit or during startup, this threshold is cut in half, providing a foldback feature. For this current limit feature to be most effective, the Thevenin resistance from FB to ground should be greater than 100kΩ. Externally Programmable Current Limit The third current limit circuit is programmed by an exter- nal resistor on RLIM. This circuit works by mirroring the input current in switch A, averaging it by means of the external RC network on RLIM, and comparing the resulting voltage with an internal reference. If the voltage on RLIM starts to exceed 0.95V, a Gm amplifier will clamp VC, lowering VOUT to maintain control of the input current. This allows the user to program a maximum average input current, for applications such as USB, where the current draw from the bus must be limited to 500mA. The resistor and capacitor values are determined by the following equations: R VV I C R LIM k IN OUT IN AMPS LIM F LIM k () () () () •. •– . Ω µ Ω = + () ⎛ ⎝ ⎜ ⎜ ⎞ ⎠ ⎟ ⎟ ≥ 70 0 86 2 40 01 |
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