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ADM1041ARQ-REEL Datasheet(PDF) 50 Page - Analog Devices |
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ADM1041ARQ-REEL Datasheet(HTML) 50 Page - Analog Devices |
50 / 64 page ADM1041 Rev. A | Page 50 of 64 Table 36. Register 1Bh, Sel CBD/SMBAlert2. Power-On Default from EEPROM Register 811Bh during Power-Up. Bit No. Name R/W Description 7 selcbd2 <7> R/W VDDOK b (inverted) 6 selcbd2 <6> R/W mfg1 5 selcbd2 <5> R/W mfg2 4 selcbd2 <4> R/W mfg3 3 selcbd2 <3> R/W mfg4 2 selcbd2 <2> R/W m_cbd_w Microprocessor Control of CBD 1 selcbd2 <1> R/W mfg5 0 selcbd2 <0> R/W Not used. Table 37. Register 1Ch, Manufacturer’s ID. Power-On Default 41h. Bit No. Name R/W Description 7–0 Manufacturer’s ID Code R This register contains the manufacturer’s ID code for the device. It is used by the manufacturer for test purposes and should not be read from or written to in normal operation. Table 38. Register 1Dh, Revision Register. Power-On Default 01h. Bit No. Name R/W Description 7–4 Major Revision Code R These 4 bits denote the generation of the device. 3–0 Minor Revision Code R These 4 bits contain the manufacturer’s code for minor revisions to the device. Rev 0 = 0h, Rev 1 = 1h, and so on. This register is used by the manufacturer for test purposes. It should not be read from or written to in normal operation. Table 39. Register 2Ah, Status1 Mirror. Power-On Default 00h. These flags are cleared by a register read, provided the fault no longer persists. Bit No. Name R/W Description 7 ovfault_L R Overvoltage fault has occurred. 6 uvfault_L R Undervoltage fault has occurred. 5 ocpto_L R Overcurrent has occured and timed out (ocpf is in Status3). 4 mfg1_L R MON1 flag. 3 mfg2_L R MON2 flag. 2 mfg3_L R MON3 flag. 1 mfg4_L R MON4 flag. 0 mfg5_L R MON5 flag. Note that latched bits are clocked on a low-to-high transmission only. Also note that these register bits are cleared when read via the SMBus, except if the fault is still present. It is recommended to read the register again after the faults disappear to ensure reset. |
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