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ADM1041ARQ Datasheet(PDF) 55 Page - Analog Devices |
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ADM1041ARQ Datasheet(HTML) 55 Page - Analog Devices |
55 / 64 page ADM1041 Rev. A | Page 55 of 64 APPENDIX A—CONFIGURATION TABLE This table is included for users to program the part by function, rather than by register. Table 45. Description Bit No. Name Bit Bit Bit Option Chip address is 1010xxx. Second address bit (EEPROM programmable). 1 add1 b1 ADD0 xxx Target device 0 L 000 0 0 H 001 1 0 Z 100 4 First address bit: ADD0 = L, pin to ground. 1 L 010 2 ADD0 = H, pin to VDD. 1 H 011 3 ADD0 = Z, pin open. 1 Z 101 5 Broadcast address. X X 111 ALL Config AC_OKLink and PSONLink. 0 i2cmb b0 Mode 0 Normal SMBus, microprocessor 1 SCL = AC_OK Link SDA = PSON Link 6 up_AC_OK_m b6 Mode 0 Hardware ACSENSE Configure ACSENSE to be hardware derived or from an SMBus command. 1 Microprocessor support via SMBus 7 up_pson_m b7 Mode 0 Hardware PS_ON Configure PSON to be hardware derived or from an SMBus command. 1 Micorporcessor support via SMBus 4 uvbm b4 Mode 0 UVB follows AC_OKLink Configure UV blanking to be internally derived or from AC_OKLink. (Set opposite to i2cmb). 1 UVB follows ACSENSE 7–0 selcbd1 bn signal 7 ovfault Build FAULT or SMBAIert signal. Allows a composite interrupt to be constructed by ORing up to 15 different signals. 6 uvfault 5 ocpt0 (ridethough timed out) 4 acsnsb 3 ocpf This uses the CBD pin. 2 otp (mov5) 1 orfetokb m_cbd_w is a µP writable bit. 0 Share_OKb 7–1 selcbd2 7 VDDOK b 6 mfgl 5 mfg2 4 mfg3 3 mfg4 2 m_cbd_w 1 mfg5 0 Not used |
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