SN65LVDS150

MuxIt

™ PLL FREQUENCY MULTIPLIER

SLLS443 – DECEMBER 2000

2

POST OFFICE BOX 655303

description (continued)

The design of the SN65LVDS150 allows it to be used at either the transmit end or the receive end of the MuxIt

serial link. The differential clock reference input (CRI) is driven by the system’s parallel data clock when at the

source end of the link, or by the link clock when at the destination end of the link. The differential clock reference

input may be driven by either an LVDS differential signal, or by a single ended clock of either polarity. For

VT, is provided on a pin adjacent the differential CRI pins for convenience when the input is used in a

single-ended mode.

The multiplied clock output (MCO) is an LVDS differential signal used to drive the high-speed shift registers in

either the SN65LVDS151 serializer-transmitter or the SN65LVDS152 receiver-deserializer. The link clock

reference output (LCRO) is an LVDS differential signal provided to the SN65LVDS151 serializer-transmitter for

transmission over the link.

below 1.5 V, or when EN is low, the device is in a low power disabled state and the MCO and LCRO differential

outputs are enabled and operating to specifications. The link clock reference output enable input (LCRO_EN)

is used to turn off the LCRO output when it is not being used. A band select input (BSEL) is used to optimize

parameter in the switching characteristic table includes details on the MCO frequency and choices of BSEL and

M.

block diagram

Frequency

Phase

Detector

VCO

Divide by M

M1 M2

M3 M4

M5

LVO

MCO+

MCO–

LCRO+

LCRO–

CRI+

CRI–

BSEL

EN

LCRO_EN

Ref.

Gen.

VT