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IDT71V3548S Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT71V3548S
Description  256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT71V3548S Datasheet(HTML) 1 Page - Integrated Device Technology

 
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MAY 2002
DSC-5296/03
1
©2002 Integrated Device Technology, Inc.
Pin Description Summary
Description
The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or
Zero Bus Turnaround.
Features
x
x
x
x
x
256K x 18 memory configurations
x
x
x
x
x
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
x
x
x
x
x
ZBTTM Feature - No dead cycles between write and read
cycles
x
x
x
x
x
Internally synchronized output buffer enable eliminates the
need to control
OE
x
x
x
x
x
Single R/
W (READ/WRITE) control pin
x
x
x
x
x
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x
x
x
x
x
4-word burst capability (interleaved or linear)
x
x
x
x
x
Individual byte write (
BW1 - BW4) control (May tie active)
x
x
x
x
x
Three chip enables for simple depth expansion
x
x
x
x
x
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
x
x
x
x
x
Optional Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
x
x
x
x
x
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
A0-A17
Address Inputs
Input
Synchronous
CE1, CE2, CE2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance burst addre ss / Load new address
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O0-I/O15, I/OP1-I/OP2
Data Input / Output
I/O
Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
Static
VSS
Ground
Supply
Static
5296 tbl 01
IDT71V3548S
IDT71V3548SA
256K x 18
3.3V Synchronous ZBT SRAM
3.3V I/O, Burst Counter
Pipelined Outputs
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71V3548 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
to disable the outputs at any given time.
A Clock Enable (
CEN) pin allows operation of the IDT71V3548
to be suspended as long as necessary. All synchronous inputs are
ignored when (
CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (
CE1, CE2, CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
asserted when ADV/
LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
The IDT71V3548 has an on-chip burst counter. In the burst
mode,theIDT71V3548canprovidefourcyclesofdataforasingleaddress
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence. The ADV/
LD signal is used to load a new external address
(ADV/
LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
TheIDT71V3548SRAMsutilizeIDT's latesthigh-performanceCMOS
process and are packaged in a JEDEC standard 14mm x 20mm 100- pin
plastic thin quad flatpack (TQFP) as well as a 119 ball grid array (BGA)
and 165 fine pitch ball grid array (fBGA).


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