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IDT71V3548S Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT71V3548S
Description  256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT71V3548S Datasheet(HTML) 6 Page - Integrated Device Technology

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IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K x 18, 165 fBGA
1
2
34
56
789
10
11
ANC(2)
A7
CE1
BW2
NC
CE2
CEN
ADV
/LD
NC(2)
A8
A10
BNC
A6
CE2
NC
BW1
CLK
R/
W
OE
NC(2)
A9
NC(2)
CNC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP1
DNC
I/O8
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O7
ENC
I/O9
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O6
FNC
I/O10
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O5
GNC
I/O11
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O4
HVDD(1)
VDD(1)
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
NC/ZZ(5)
JI/O12
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
NC
KI/O13
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O2
NC
LI/O14
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
NC
MI/O15
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O0
NC
NI/OP2
NC
VDDQ
VSS
NC/
TRST(3,4)
NC
VDD(1)
VSS
VDDQ
NC
NC
PNC
NC(2)
A5
A2
NC/TDI(3)
A1
NC/TDO(3)
A11
A14
A15
NC
R
LBO
NC(2)
A4
A3
NC/TMS(3)
A0
NC/TCK(3)
A12
A13
A16
A17
5296 tbl 25
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is
≥ VIH.
2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M, and 288M respectively respectively.
3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
4.
TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin H11 supports ZZ (sleep mode) on the latest die revision.


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