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ADSP-TS201S Datasheet(PDF) 2 Page - Analog Devices |
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ADSP-TS201S Datasheet(HTML) 2 Page - Analog Devices |
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Rev. PrH | Page 2 of 40 | December 2003 ADSP-TS201S Preliminary Technical Data TABLE OF CONTENTS General Description ................................................. 3 Dual Compute Blocks ............................................ 4 Data Alignment Buffer (DAB) .................................. 4 Dual Integer ALU (IALU) ....................................... 4 Program Sequencer ............................................... 5 Interrupt Controller ........................................... 5 Flexible Instruction Set ........................................ 5 DSP Memory ....................................................... 5 External Port (Off-Chip Memory/Peripherals Interface) ................ 6 Host Interface ................................................... 6 Multiprocessor Interface ...................................... 7 SDRAM Controller ............................................ 7 EPROM Interface .............................................. 7 DMA Controller ................................................... 7 Link Ports (LVDS) ................................................ 8 Timer and General-Purpose I/O ............................... 9 Reset and Booting ................................................. 9 Clock Domains .................................................... 9 Power Domains .................................................... 9 Filtering Reference Voltage and Clocks ...................... 9 Development Tools ............................................. 10 Designing an Emulator-Compatible DSP Board (Target) 11 Additional Information ........................................ 11 Pin Function Descriptions ........................................ 12 Strap Pin Function Descriptions ................................ 19 ADSP-TS201S—Specifications ................................... 21 Recommended Operating Conditions ...................... 21 Electrical Characteristics ....................................... 21 Absolute Maximum Ratings ................................... 22 ESD Sensitivity ................................................... 22 Timing Specifications ........................................... 23 General AC Timing .......................................... 23 Link Port Low-Voltage, Differential-Signal (LVDS) Electrical Characteristics and Timing ................. 27 Link Port—Data Out Timing ........................... 28 Link Port—Data In Timing .............................. 31 Output Drive Currents ......................................... 32 Test Conditions .................................................. 33 Output Disable Time ......................................... 33 Output Enable Time ......................................... 34 Capacitive Loading ........................................... 34 Environmental Conditions .................................... 36 Thermal Characteristics ..................................... 36 576-Ball BGA_ED Pin Configurations ......................... 36 Outline Dimensions ................................................ 40 Ordering Guide ..................................................... 40 REVISION HISTORY Revision PrH: • Applies corrections and additional information (includ- ing information on 600 MHz parts) to VREF Filtering Scheme (page 10), SCLK_VREF Filtering Scheme (page 10), Drive Strength/Output Impedance Selection (page 19), Recommended Operating Conditions (page 22), Electrical Characteristics (page 22), Reference Clocks (page 24), Power-Up Reset Timing (page 25), AC Signal Specifications (page 26), Link Port—Data Out Timing (page 29), Link Port—Data In Timing (page 32), and Ordering Guide (page 42). • Provides unused pin termination data in Pin Function Descriptions (page 13). • Changes pins R2 and R3 to NC in 576-Ball (25 mm × 25 mm) BGA_ED Pin Assignments (page 38). |
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