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ADSP-TS201S Datasheet(PDF) 6 Page - Analog Devices

Part No. ADSP-TS201S
Description  TigerSHARC-R Embedded Processor
Download  40 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-TS201S Datasheet(HTML) 6 Page - Analog Devices

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Rev. PrH
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Page 6 of 40
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December 2003
ADSP-TS201S
Preliminary Technical Data
EXTERNAL PORT
(OFF-CHIP MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS201S processor’s external port provides the DSP’s
interface to off-chip memory and peripherals. The 4G word
address space is included in the DSP’s unified address space.
The separate on-chip buses—four 128-bit data buses and four
32-bit address buses—are multiplexed at the SOC interface and
transferred to the external port over the SOC bus to create an
external system bus transaction. The external system bus pro-
vides a single 64-bit data bus and a single 32-bit address bus.
The external port supports data transfer rates of 1G bytes per
second over the external bus.
The external bus can be configured for 32- or 64-bit, little-
endian operations. When the system bus is configured for 64-bit
operations, the lower 32 bits of the external data bus connect to
even addresses, and the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high-
order address lines to generate memory bank select signals.
The ADSP-TS201S processor provides programmable memory,
pipeline depth, and idle cycle for synchronous accesses, and
external acknowledge controls to support interfacing to pipe-
lined or slow devices, host processors, and other memory-
mapped peripherals with variable access, hold, and disable time
requirements.
Host Interface
The ADSP-TS201S processor provides an easy and configurable
interface between its external bus and host processors through
the external port. To accommodate a variety of host processors,
Figure 3. ADSP-TS201S Memory Map
RESERVED
RESERVED
INTERNAL REGISTERS (UREG S)
INTERNAL MEMO RY BLOCK 4
INTERNAL MEMORY BLOCK 2
INTERNAL MEMORY BLOCK 0
0x03FFFFFF
0X001E0000
0x001E03FF
0x000DFFFF
0x000C0000
0x0009FFFF
0x00080000
0x0005FFFF
0x00040000
0x0001FFFF
0x00000000
INTERNAL SPACE
PROCESSO R ID 7
PROCESSO R ID 6
PROCESSO R ID 5
PROCESSO R ID 4
PROCESSO R ID 3
PROCESSO R ID 2
PROCESSO R ID 1
PROCESSO R ID 0
BROADCAST
HOST (
MSH)
BANK 1 (
MS1)
BANK 0 (
MS0)
MSSD BANK 0 (
MSSD0)
INTERNAL MEMORY
0x50000000
0x40000000
0x38000000
0x30000000
0x2C000000
0x28000000
0x24000000
0x20000000
0x1C000000
0x18000000
0x14000000
0x10000000
0X0C000000
0x03FFFFFF
0x00000000
GLOBAL SPACE
0xFFFFFFFF
EACH IS A COPY
OF INTERNAL SPACE
RESERVED
INTERNAL MEMO RY BLOCK 6
INTERNAL MEMO RY BLOCK 8
0x0011FFFF
0x00100000
INTERNAL MEMO RY BL OCK 10
0x0015FFFF
0x00140000
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SOC REGISTERS (UREGS)
0X001F0000
0x001F03FF
MSSD BANK 1 (
MSSD1)
MSSD BANK 2 (
MSSD2)
MSSD BANK 3 (
MSSD3)
0x60000000
0x70000000
0x80000000
RESERVED
RESERVED
RESERVED
RESERVED
0x54000000
0x44000000
0x64000000
0x74000000


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