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ADSP-TS201S Datasheet(PDF) 4 Page - Analog Devices |
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ADSP-TS201S Datasheet(HTML) 4 Page - Analog Devices |
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4 / 40 page 
Rev. PrH | Page 4 of 40 | December 2003 ADSP-TS201S Preliminary Technical Data the DSP does not perform instruction re-ordering at runtime— the programmer selects which operations will execute in parallel prior to runtime—the order of instructions is static. With few exceptions, an instruction line, whether it contains one, two, three, or four 32-bit instructions, executes with a throughput of one cycle in a ten-deep processor pipeline. For optimal DSP program execution, programmers must follow the DSP’s set of instruction parallelism rules when encoding an instruction line. In general, the selection of instructions that the DSP can execute in parallel each cycle depends on the instruc- tion line resources each instruction requires and on the source and destination registers used in the instructions. The program- mer has direct control of three core components—the IALUs, the compute blocks, and the program sequencer. The ADSP-TS201S processor, in most cases, has a two-cycle execution pipeline that is fully interlocked, so—whenever a computation result is unavailable for another operation depen- dent on it—the DSP automatically inserts one or more stall cycles as needed. Efficient programming with dependency-free instructions can eliminate most computational and memory transfer data dependencies. In addition, the ADSP-TS201S processor supports SIMD opera- tions two ways—SIMD compute blocks and SIMD computations. The programmer can load both compute blocks with the same data (broadcast distribution) or different data (merged distribution). DUAL COMPUTE BLOCKS The ADSP-TS201S processor has compute blocks that can exe- cute computations either independently or together as a Single- Instruction, Multiple-Data (SIMD) engine. The DSP can issue up to two compute instructions per compute block each cycle, instructing the ALU, multiplier, shifter, or CLU to perform independent, simultaneous operations. Each compute block can execute eight 8-bit, four 16-bit, two 32-bit, or one 64-bit SIMD computations in parallel with the operation in the other block. The compute blocks are referred to as X and Y in assembly syn- tax, and each block contains four computational units—an ALU, a multiplier, a 64-bit shifter, a 128-bit CLU—and a 32- word register file. • Register File—Each Compute Block has a multiported 32- word, fully orthogonal register file used for transferring data between the computation units and data buses and for storing intermediate results. Instructions can access the registers in the register file individually (word-aligned), in sets of two (dual-aligned), or in sets of four (quad-aligned). • ALU—The ALU performs a standard set of arithmetic operations in both fixed- and floating-point formats. It also performs logic operations. • Multiplier—The multiplier performs both fixed- and float- ing-point multiplication and fixed-point multiply and accumulate. • Shifter—The 64-bit shifter performs logical and arithmetic shifts, bit and bitstream manipulation, and field deposit and extraction operations. • Communications Logic Unit (CLU)—This is a 128-bit unit provides Trellis Decoding (for example, Viterbi and Turbo decoders) and executes complex correlations for CDMA communication applications (for example chip-rate and symbol-rate functions). Using these features, the compute blocks can: • Provide 8 MACs per cycle peak and 7.1 MACs per cycle sustained 16-bit performance and provide 2 MACs per cycle peak and 1.8 MACs per cycle sustained 32-bit perfor- mance (based on FIR) • Execute six single-precision floating-point or execute twenty-four 16-bit fixed-point operations per cycle, pro- viding 3 GFLOPS or 12.0 GOPS performance • Perform two complex 16-bit MACs per cycle • Execute eight Trellis butterflies in one cycle DATA ALIGNMENT BUFFER (DAB) The DAB is a quad-word FIFO that enables loading of quad- word data from nonaligned addresses. Normally, load instruc- tions must be aligned to their data size so that quad words are loaded from a quad-aligned address. Using the DAB signifi- cantly improves the efficiency of some applications, such as FIR filters. DUAL INTEGER ALU (IALU) The ADSP-TS201S processor has two IALUs that provide pow- erful address generation capabilities and perform many general- purpose integer operations. The IALUs are referred to as J and K in assembly syntax and have the following features: • Provides memory addresses for data and update pointers • Supports circular buffering and bit-reverse addressing • Performs general-purpose integer operations, increasing programming flexibility • Includes a 31-word register file for each IALU As address generators, the IALUs perform immediate or indi- rect (pre- and post-modify) addressing. They perform modulus and bit-reverse operations with no constraints placed on mem- ory addresses for the modulus data buffer placement. Each IALU can specify either a single-, dual-, or quad-word access from memory. The IALUs have hardware support for circular buffers, bit reverse, and zero-overhead looping. Circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal processing, and they are commonly used in digital filters and Fourier transforms. Each IALU pro- vides registers for four circular buffers, so applications can set up a total of eight circular buffers. The IALUs handle address pointer wraparound automatically, reducing overhead, increas- ing performance, and simplifying implementation. Circular buffers can start and end at any memory location. |
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