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Z80182 Datasheet(PDF) 45 Page - Zilog, Inc. |
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Z80182 Datasheet(HTML) 45 Page - Zilog, Inc. |
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45 / 326 page  Z 8018x Fam il y M PU Use r M anual 30 UM005001-ZMP0400 inserted depending on the programmed value in IWI1 and IWI0. Refer to Table 4. WAIT Input and RESET During RESET, MWI1, MWI0 IWI1 and IWI0, are all 1, selecting the maximum number of Wait States (TW) (three for memory accesses, four for external I/O accesses). Table 4. Wait State Insertion IW I1 IW I0 Th e Num be r of W ait States For e xte rnal I/O re gis te rs accesses For inte rnal I/0 re gis te rs accesses For INT0 inte rrupt ack now l e dge cycl es wh e n M 1 is Low For INT1, INT2 and inte rnal inte rrupts ack now l e dge cycl es (Note 2) For NM I inte rrupt ack now l e dge cycl es wh e n M 1 is Low (Note 2) 0 0 1 0 (Note 1) 2 2 0 0 1 2 4 1 0 3 5 1 1 4 6 Note: 1. For Z8X180 internal I/O register access (I/O addresses 0000H-003FH), IWI1 and IWI0 do not determine wait state (TW) timing. For ASCI, CSI/O and PRT Data Register accesses, 0 to 4 Wait States (TW) are generated. The number of Wait States inserted during access to these registers is a function of internal synchronization requirements and CPU state. All other on-chip I/O register accesses (that is, MMU, DMAC, ASCI Control Registers, for instance.) have no Wait States inserted and thus require only three clock cycles. 2. For interrupt acknowledge cycles in which M1 is High, such as interrupt vector table read and PC stacking cycle, memory access timing applies. |
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