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Z80182 Datasheet(PDF) 71 Page - Zilog, Inc. |
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Z80182 Datasheet(HTML) 71 Page - Zilog, Inc. |
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71 / 326 page  Z 8018x Fam il y M PU Use r M anual 56 UM005001-ZMP0400 Figure 24. Physical Address Transition MMU Block Diagram The MMU block diagram is depicted in Figure 25. The MMU translates internal 16-bit logical addresses to external 20-bit physical addresses. Figure 25. MMU Block Diagram Logical Address Space Physical Address Space Common Area 1 Bank Area Common Area 0 Common Base Bank Base FFFFH 0000H FFFFFH 00000H 0 + + + x y z z y x MMU Common/Bank Area Register; CBAR (8) Memory Management 8 PA12— PA19 LA12— LA15 4 MMU Common Base Register; CBR (8) MMU Bank Base Register; BBR (8) LA: Logical Address PA: Physical Address Internal Address/Data Bus Unit |
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