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Z80180 Datasheet(PDF) 72 Page - Zilog, Inc. |
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Z80180 Datasheet(HTML) 72 Page - Zilog, Inc. |
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72 / 326 page  Z 8018x Fam il y M PU Use r M anual UM005001-ZMP0400 57 Whether address translation (Figure 26) takes place depends on the type of CPU cycle as follows. • Memory Cycles Address Translation occurs for all memory access cycles including instruction and operand fetches, memory data reads and writes, hardware interrupt vector fetch, and software interrupt restarts. • I/O Cycles The MMU is logically bypassed for I/O cycles. The 16-bit logical I/O address space corresponds directly with the 16-bit physical I/O address space. The four high-order bits (A16–A19) of the physical address are always 0 during I/O cycles. Figure 26. I/O Address Translation • DMA Cycles When the Z8X180 on-chip DMAC is using the external bus, the MMU is physically bypassed. The 20-bit source and destination registers in the DMAC are directly output on the physical address bus (A0–A19). MMU Registers Three MMU registers are used to program a specific configuration of logical and physical memory. LA15 PA19 LA0 PA16 PA15 PA0 “0000” Logical Address Physical Address |
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