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M5M5V408BFP-85L Datasheet(PDF) 3 Page - Mitsubishi Electric Semiconductor

Part # M5M5V408BFP-85L
Description  4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M5M5V408BFP-85L Datasheet(HTML) 3 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI ELECTRIC
M5M5V408BFP/TP/RT/KV/KR
revision-K1.0e, ' 98.09.07
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
FUNCTION TABLE
BLOCK DIAGRAM
3
Mode
DQ
Icc
S
W
OE
Write
Read
H
L
L
L
L
X
L
H
H
H
X
X
Non selection
High-impedance
High-impedance
Active
Standby
Read
A4
A5
A6
A7
A12
A14
A16
A17
A18
A11
A9
A8
12
A0
11
A1
10
A2
9
A3
A13
25
26
27
28
8
7
6
5
4
3
2
30
1
A15
31
A10
23
DQ1
DQ2
DQ3
DQ4
VCC
(3V)
GND
(0V)
W
OE
DQ5
DQ6
DQ7
DQ8
S
24
13
14
15
17
32
22
18
19
20
21
29
16
A0 ~ A18
DQ1 ~ DQ8
S
W
OE
Vcc
GND
Address input
Data input / output
Chip select input
Write control input
Output inable input
Power supply
Ground supply
Pin
Function
Data input (D)
Active
Active
MEMORY ARRAY
524288 WORDS
x 8 BITS
CLOCK
GENERATOR
FUNCTION
The M5M5408BFP,TP,RT,KV,KR is organized as 524,288-
words by 8-bit. These devices operate on a single +2.7~3.6V
power supply, and are directly TTL compatible to both input
and output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
A write operation is executed during the S low and W low
overlap time. The address(A0~A18) must be set up before
the write cycle
A read operation is executed by setting W at a high level
and OE at a low level while S are in an active state(S=L).
When setting S at a high level, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-impedance
state, allowing OR-tie with other chips. Setting the OE at a high
level,the output stage is in a high-impedance state, and the
data bus contention problem in the write cycle is eliminated.
The power supply current is reduced as low as 0.3µA(25°C,
typical), and the memory data can be held
at +2V power
supply, enabling battery back-up operation during power failure
or power-down operation in the non-selected mode.
Data output (Q)
20
19
18
17
1
2
3
4
16
15
14
13
12
11
10
9
6
7
31
32
21
22
23
25
8
30
26
27
28
29
5
24
M5M5V408BKV/KR
M5M5V408B
FP/TP/RT
M5M5V408BKV/KR
M5M5V408B
FP/TP/RT


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