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LMH0046 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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LMH0046 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 10 page Device Description The LMH0046 HD/SD Mutli-Rate Serial Digital Video Re- clocker is used in many types of digital video signal process- ing equipment. Supported serial digital video standards are SMPTE 259M A & C and SMPTE 292M. Corresponding serial data rates are 143 Mbps, 270 Mbps, 1.483 Gbps and 1.485 Gbps. DVB-ASI data at 270 Mbps may also be re- timed. The LMH0046 retimes the serial data stream to sup- press accumulated jitter. It provides two low-jitter, differential, serial data outputs. The second output may be selected to output either serial data or a low-jitter serial data-rate clock. Controls and indicators are: serial data-rate clock or second serial data output select, manual rate select input, SD/HD rate output, lock detect output, auto/manual data bypass and output mute. Serial data inputs are CML and LVPECL compatible. Serial data and data-rate clock outputs are differential CML and produce LVPECL compatible levels. The output buffer de- sign can drive AC or DC-coupled, terminated 100 Ω differen- tial loads. The differential output level is 800 mV P-P ±10% into 100 Ω AC or DC-coupled differential loads. Logic inputs and outputs are LVCMOS compatible. The device package is a TSSOP20 with an exposed die attach pad. The exposed die attach pad is electrically con- nected to device ground (V EE) and is the negative electrical terminal for the device. This terminal must be connected to the negative power supply or circuit ground. Serial Data Inputs, Serial Data and Clock Outputs SERIAL DATA INPUT AND OUTPUTS The differential serial data input, SDI, accepts serial digital video data at the rates specified in Table 1. The serial data input is differential LVPECL compatible. These inputs are intended to be DC interfaced to devices such as the LMH0034 adaptive cable equalizer. These inputs are not internally terminated or biased. The inputs may be AC- coupled if a suitable input bias voltage is provided. The LMH0046 has two, retimed, differential, serial data out- puts, SDO and SCO/SDO2. These outputs provide low jitter, differential, retimed data to devices such as the LMH0002 cable driver or the LMH0031 deserializer. Output SCO/ SDO2 is multiplexed and can provide either a second serial data output or a serial data-rate clock output. The SCO_EN input controls the operating mode for the SCO/SDO2 output. When the SCO_EN input is high the SCO/SDO2 output provides a serial data-rate clock. When SCO_EN is low, the SCO/SDO2 output provides retimed serial data. Both differential serial data outputs, SDO and SCO/SDO2, are muted when the MUTE input is a logic low level. SCO/ SDO2 also mutes when the Bypass mode is activated when this output is operating as the serial clock output. When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite differential output levels. The CML serial data out- puts are differential LVPECL compatible. These outputs have internal 50 Ω pull-ups and are suitable for driving AC or DC-coupled, 100 Ω center-tapped, AC grounded or 100Ω un-center-tapped, differentially terminated networks. OPERATING SERIAL DATA RATES This device operates at serial data rates of 143 Mbps, 270 Mbps, 1483 Mbps and 1485 Mbps. The device does not lock to harmonics of these rates. The device does not lock and automatically enters the reclocker bypass mode for the fol- lowing data rates: 177 Mbps, 360 Mbps, and 540 Mbps. SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the corresponding serial data bit interval within 15% of the center of the data interval. Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low level. This output functions as the serial data-rate clock output when the SCO_EN input is a logic-high level. The SCO_EN input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2 enabled). SCO/SDO2 is muted when the MUTE input is a logic low level. When the Bypass mode is activated and this output is functioning as a serial clock output, the output will also be muted. Control Inputs and Indicator Outputs SERIAL DATA RATE SELECTOR The Serial Data Rate Selector (RATE [1:0]) permits the user to fix the operating serial data rate. The pins have internal pull-downs which maintain a logic-low input condition unless externally driven to a logic-high condition. This input also serves to place the device in a test mode. The codes shown in Table 1 select the desired operating serial data rate. The LMH0046 then enters either the Auto-Rate Detect mode, a single operating rate, or the test mode. Selecting the 270 Mbps rate mode may also be used when reclocking DVB- ASI data. DVB-ASI data is MPEG2 coded data that is trans- mitted in 8B10B coding. The device should reclock this data without harmonic locking. TABLE 1. Data Rate Select Input Codes Rate [1:0] Code Data Rate or Mode Comments 00 Auto-Rate Detect mode 143 Mbps rate operation supported only in ARD mode 01 270 Mbps May be used to support DVB-ASI operation 10 1483/1485 Mbps LOCK DETECT The Lock Detect (LD) output, when high, indicates that data is being received and the PLL is locked. LD may be con- nected to the MUTE input to mute the data and clock outputs when no data signal is being received. See Table 2. www.national.com 7 |
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